Expand your own FPGA horizons with our detailed technical guides
FPGA Horizons Lab Notes deliver practical engineering guidance, hands‑on walkthroughs, and reproducible workflows for real‑world FPGA design challenges. Each Lab Note focuses on a single, clearly defined technique and shows you how to implement it using real tools, real constraints, and real hardware. They’re written by engineers, for engineers, to help you build, debug, and verify FPGA designs with confidence.
Understanding ADC performance: The foundations of analogue‑to‑digital conversion
The world is analog, but it is best processed digitally, where the processing is immune from analog effects such as component tolerance, aging, temperature effects and drift. To enable that, we must implement a conversion between the analog and digital domains using ADC and DAC convertors. The behavior of these converters is not as simple as one might at first consider, however. This Lab Note outlines, explains and discusses the performance considerations we need to understand to be able to assess how an ADC or DAC will operate in practice.
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Understanding DAC performance: Core principles and dynamic testing
In this partner Lab Note to Understanding ADC performance: The foundations of analog‑to‑ digital conversion, we turn the problem around and test a DAC. Here, the roles are reversed: the FPGA is now the signal source, generating the test waveform digitally, and the measurement instrument sits on the analog side. This Lab Note demonstrates how it gives us the ability to generate a perfectly coherent stimulus, drive the DAC under controlled conditions, and test its dynamic behavior directly from the resulting spectrum.
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Building a secure FPGA architecture: Deterministic, reliable, and resilient FPGA design
Secure FPGA design is about more than encryption or bitstream protection. It requires disciplined engineering across configuration, clocking, reset, RTL structure, I/O behavior, and radiation mitigation. This Lab Note shows how to build FPGA architectures that start up predictably, resist both intentional and unintentional faults, and behave reliably in real‑world environments. Learn how threat modelling, safe CDC, hardened I/O, and robust configuration practices can help you create deterministic, resilient FPGA designs.
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Understanding FPGA I/O standards: Choosing the right signaling for your design
Modern FPGAs support a wide range of I/O standards, ranging from basic LVCMOS GPIO to multi-gigabit differential links. Each brings its own expectations for voltage levels, termination, impedance, noise tolerance, and switching behavior. Discover how to choose and apply FPGA I/O standards for real-world digital interfaces, covering both on-board and off-board signaling paths, and focusing on the electrical behaviors that matter in practice.
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FPGA first power-on: A structured approach for early hardware validation and debug
In this Lab Note we explore how to power-on an FPGA board safely and predictably. The emphasis is on the practical steps involved in early validation and looks at how to analyze failure modes, confirm margins, check component stress, prepare rails, and activate subsystems in a controlled sequence. It provides a clear, structured approach for powering and debugging new FPGA hardware, in order to reduce risk, accelerate validation, and ensure the board behaves as intended.
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