London 26 agenda

8.30 – 9.00

Arrival / Registration / Breakfast

9.00 – 9.15

Welcome

9.15 – 10.00

Keynote: System-Level Design meets AI-Driven Workflows in Modern FPGA Embedded Systems

AMD
Kirk Saban, CVP – Embedded Products, Software & Solutions

Designing embedded applications demands an evolving system-level perspective, where workloads are aligned to the right compute architecture and design flows are optimized for faster, higher-quality implementation. This keynote takes a top-down view of modern design, spanning FPGA flexibility, embedded processing, and heterogeneous compute, while examining how advances in AI-driven tools are reshaping FPGA workflows through co-pilot-style interaction for design and verification. Together, these trends are enabling architects and FPGA designers to move from concept to implementation with greater speed and confidence. This session will explore what that means in practice.

10.10 – 10.40

Practical Security Fundamentals for FPGA Engineers

Lattice Semiconductor
Matt Holdsworth, Senior FAE

Security is increasingly becoming a core design requirement, even for engineers who do not specialize in it. This session introduces the essential security concepts; trust, privacy, integrity, and availability, in a way that connects directly to FPGA development and real‑world system architecture. Instead of focusing on cryptography or abstract theory, we look at how these principles influence system design and device selection. Attendees will gain a practical understanding of how security requirements will impact their own designs and how hardware‑based security can significantly strengthen the resilience of FPGA‑centric systems.

Leading Low Power, High Speed Small Form Factor System Devices

Efinix
Harald Werner, VP Sales EMEA and Managing Director EMEA

Efinix offers FPGAs in a small form factor that can serve as system controllers, ideally suited for demanding edge applications. The new System in Package (SiP) devices further simplify integration by combining multiple advantages such as lower power consumption, a smaller footprint, and easier PCB integration. Examples include the Ti125 SIP with integrated HyperRAM and the Ti135 SIP with integrated LPDDR4. These devices deliver unprecedented performance in terms of speed and power efficiency. This presentation provides a detailed overview of the new devices and their features, along with exemplary applications.

10.50 – 11.20

The Cyber Resilience Act is here: Are your FPGAs ready?

Microchip
Ian Pearson, Principal Field Applications Engineer

This presentation explores the EU Cyber Resilience Act (CRA) and its far-reaching impact on connected products entering the European market. It explains the CRA’s essential requirements, life-cycle-based security expectations, and mandatory vulnerability-management processes. The session outlines risk-based product classifications, documentation and reporting obligations, and the role of emerging horizontal and vertical standards in demonstrating compliance. It also clarifies the responsibilities for manufacturers, including support and security update requirements, and highlights how the CRA applies to both new and legacy products. Pearson will also outline how Microchip Technology is setting the benchmark for secure FPGA design, supporting customers with robust security architectures, comprehensive documentation, and proven, security-focused components— enabling faster, more confident compliance with the CRA.

Making Electronics Under Pressure

XJTAG
Bob Storey, Chief Technology Officer

Throughout the whole product development lifecycle there is more pressure than ever to move fast and do it right first time. With new PCB technologies such as High-Density Interconnect, blind vias and embedded components becoming increasingly common we will discuss test methodologies and architectures at both device and board level which can help engineers make the right choice for their needs. There is no golden ticket!

11.20 – 11.40

Break

11.40 – 12.00

AMD Versal AI Engine Architecture and DSP Application Development Flow

Avnet Silica
Dr Baha Hashimi, Embedded Systems Specialist

5G wireless communication systems and high resolution medical imaging are compute intensive applications. This session will demonstrate how the intense computation needed for these applications can be accelerated using the AI Engines in Versal to perform DSP workloads. This presentation provides an overview of the AI Engine architecture and the development flow for creating efficient DSP applications, covering key aspects such as programming methodology, functional verification and validation using AMD development tools. enabling attendees to understand how they are able to develop DSP for AIE solutions for their own applications.

Bringing Software’s Proven Lessons to Modern FPGA Application Design

Eccelerators
Denis Vasilik, Technical Director

Have you ever wondered whether applications really need a processor? Is firmware, an operating system, and a driver stack always required – or is that simply how we learned to structure systems?

What if application logic could be implemented directly on an FPGA, with the same level of structure and clarity we expect from software development, but without firmware overhead, operating systems, or CPUs? Livt challenges this long-standing assumption by enabling complete applications to be built directly in hardware. A processor becomes an optional integration choice rather than a prerequisite, enabling simpler systems, lower latency, and more deterministic behavior – while retaining application-level structure.

In software development, engineers rarely work at the processor or assembler level, reinventing basic functionality for every project. Progress became possible because higher-level abstractions, shared libraries, frameworks, and reusable building blocks emerged. FPGA development, by contrast, is still largely performed at a low level. Many teams maintain their own sets of abstractions, engineers repeatedly solve the same problems, and designs quickly hit a wall of complexity as systems grow.

Livt addresses this by making application development on FPGAs possible. It is built around hardware-native semantics – explicit state machines, multiplexing, and concurrency – which map directly to HDL, while enabling reuse at multiple layers. Language constructs support encapsulation, interfaces, and composition. On top of that, developers work with packages and frameworks instead of large, monolithic IP blocks. These layers can be stacked, reused, and evolved, allowing functionality to grow incrementally rather than exponentially in complexity – and providing the structure required for modern, tool-assisted and guided development workflows.

Livt invites engineers to rethink FPGA design as true application development in hardware – enabling complex, structured systems to be built directly on silicon, with or without a processor.

During the session, you will see an example application of a secure webservice – no OS, no CPU, no attacks. Livt!

12.10 – 12.30

Beyond the Lab Bench: Boosting FPGA Development Productivity with Remote & Hybrid FPGA prototyping

Exostiv Labs
Frederic Leens, CEO and Founder

For many companies, limited access to high-end FPGA boards, long compile times, and the physical constraints of lab-based debugging create a significant ‘hardware bottleneck’ – particularly early in the design cycle. This session challenges the traditional ‘one-engineer, one-board’ model by exploring the shift toward Remote and Hybrid FPGA Prototyping.

To succeed, such a model must bridge the ‘visibility gap’ inherent to off-site hardware. This requires delivering lab-quality signal tracing and stimulus generation through an intuitive interface that integrates into the engineer’s verification and validation workflow. During this session, the audience will learn about Exostiv Labs’ current experimentation in building a remote and hybrid prototyping proposition specifically designed to meet the needs of the FPGA engineering community

Designing and Verifying FPGAs for Spaceflight Applications

Phixos
Jack Sampford, Chief Firmware Engineer

FPGAs are used for a multitude of purposes in spaceflight applications such as image processing, spacecraft control, and communications. They are commonly used in both low earth orbit (LEO) and geostationary orbit (GEO) satellites, with each presenting a unique operational environment and lifespan considerations. This technical session focuses particularly on the challenges faced when designing and implementing FPGAs for geostationary satellites including extreme temperatures, technology limitations, and radiation effects. It also covers the mitigations which can be put in place to account for these challenges, and the verification and validation techniques which can be used to give confidence in these mitigations.

12.40 – 13.00

RFSoC at the Edge

Molex
Craig Petrie, Vice President

Molex uses FPGA and RFSoC devices, tools and IP to help customers solve a variety of challenging application requirements. In this presentation, Molex will provide insight into how customers are using FPGA technology within complex systems at the edge and within the data centres to meet the needs of emerging compute, network, storage and sensor processing workloads.

Building an Open FPGA Module Standard: Lessons Learned, Trade-offs, and Real-World Design Decisions

Standardization Group for Embedded Technologies (SGET)
Ansgar Hein, Chairman of the Board

FPGA projects rarely fail because of logic design. They fail because everything around the FPGA has to be rebuilt, again and again.

Form factors, pinouts, thermal concepts, and carrier board architectures are typically defined from scratch for each project. This leads to long development cycles, limited reuse, and tightly coupled vendor ecosystems.

While modular approaches are well established in CPU-based systems, applying the same principles to FPGA designs turns out to be significantly more complex.

This talk explores what it takes to move from one-off FPGA designs to modular, reusable system architectures, based on the development of the Open Harmonized FPGA Module (oHFM).

Instead of presenting the standard itself, the focus is on the engineering decisions behind it:

Why FPGA modularization is fundamentally harder than CPU-based COM approaches
How different integration models lead to conflicting requirements
Signal grouping, scalability, and system-level constraints
Mechanical, thermal, and high-speed interface trade-offs
What worked, what didn’t, and where compromises were necessary

One key outcome was the realization that a single module concept cannot cover the full range of FPGA use cases, leading to two distinct integration approaches with different constraints and trade-offs.

Attendees will gain a practical understanding of how to approach modular FPGA system design, what pitfalls to avoid, and how to make better architectural decisions when designing scalable FPGA-based products.

13.00 – 14.00

Lunch

14.00 – 14.20

A Modular Solution for Versal RF Deployment

Alpha Data
Kevin Roth, Product Director

In this talk, Alpha Data will present the modular approach taken to solve the difficulties in delivering Versal RF technology based systems into development and deployable applications. At the core of the approach is the use of a system on module, to allow an economic deployment in a variety of form factors. Digital carrier base boards provide power and digital connection in industry standard form factors. The variety of analogue requirements is handled separately on a different daughter boards to maximize flexibility and standardization of modules. To successfully design, reliable products with such high fidelity analogue performance requires extensive simulation as well as physical prototyping and testing. The highlights of this design process will be presented. The product is not the hardware alone, and highlights of the software development process used to develop the supporting FPGA firmware, IP examples, and development kit will also be presented.

From Concept to Certification: Design Paradigms and Countermeasures for Secure FPGA Systems

TÜV Informationstechnik GmbH
Nick Theisejans, Senior Expert Hardware & Embedded Security

As FPGAs increasingly become the backbone of space, aerospace, military, and mission-critical applications, new regulatory frameworks strictly demand verified, hardware-level security. However, FPGAs are historically difficult to certify. The main problem is that traditional certification approaches often rely on attacker models assuming physical inaccessibility to the FPGA i.e., the classic Hardware Security Module (HSM) approach. This assumption completely fails in modern edge and field deployments. Drawing on practical insights from an independent security evaluation laboratory, this talk explores the concrete system-engineering challenges of bridging this certification gap and making an FPGA system truly certifiable without assumptions on the environment.

Moving beyond theoretical vulnerabilities, we will detail the demands placed on hardware architects and what core security functionalities – such as secure boot, rollback protection, random number generation and cryptographic primitives – an FPGA architecture must inherently provide to be certifiable. The presentation will provide a twofold breakdown: Logical exploits on the architectural level versus physical threats like side-channel analysis and fault injection. Using architectural block diagrams and system-level concepts, we will dive into how to design effective countermeasures that can withstand these specific real-world attacks. Finally, we will highlight the critical role of a secure supply chain, illustrating why even the most resilient on-chip architecture fails without secure production and provisioning lifecycles.

Ultimately, hardware architects and system engineers will leave with a clear roadmap of evolving security requirements, gaining actionable insights into designing and implementing a certifiable FPGA architecture.

14.30 – 14.50

FPGA Security demystified

Altera
Graham McKenzie, Principal Field Application Engineer

With the emergence of the Cyber Resilience Act and other industry inflection points, design security is becoming more important and certainly more talked about. But what is design security, what features are available in FPGAs and how do they help secure my design and my product?

During this talk, we will explore the fundamentals of design security, examine how security features have evolved, and discuss how Altera is prepared for a post-quantum world. We will review specific FPGA security features, the threats they mitigate, and how they are implemented, so that security becomes less of a mystery and more of routine aspect of FPGA engineering.

Learn about IEEE 1588/PTP timing synchronization and distribution within FPGAs, SoCs, and RFSoCs

Fidus
Matthew Fransham, Lead Solutions Architect

In this talk, Fidus dives into a compelling discussion on implementing time synchronization and clock distribution in today’s time-reliant embedded systems. They will discuss IEEE 1588/PTP implementations and how the functionality is commonly enabled either solely within, or jointly between, FPGAs, processors, and/or dedicated timing silicon. They’ll share experience of using the locked, recovered clock to generate synchronized sampling clocks for both onboard and multi-board RF/analog frontends (i.e., ADCs and DACs).

15.00 – 15.20

Common Framework for FPGA-based Hardware Root of Trust

Xiphera
Valtteri Allekotte, Field Application Engineer

A hardware root-of-trust (HW-RoT) is an essential component for establishing and maintaining digital trust on a computing platform. Solutions offering a range of HW-RoT services for a host system include TPM (Trusted Platform Modules), DICE (Device Identification Composition Engine), and open source implementations such as OpenTitan and Caliptra. Verification and validation of these may prove challenging, especially when applied in high-security assurance scenarios. In this presentation we establish a base for essential HW-RoT functions and requirements, and propose a foundation and architecture for building an FPGA-based Root-of-Trust for enhanced security, lower power consumption, crypto agility, as well as streamlined testing and validation.

Future-Proofing the Edge: Strategies for Scalable System Design

Enclustra
Roland Paul, Senior Director Sales

Today’s edge computing applications require diverse architectures to balance performance, power consumption, and cost. Modern FPGA-based technologies, such as AMD Versal™ AI Edge Gen2, offer a heterogeneous mix of engines – including scalar processors (Arm cores), video processors (ISP/VCU), AI accelerators (ML/Tensor cores), and adaptable logic. However, since few applications require every feature, and requirements often evolve throughout a product’s lifecycle, a rigid design can be a liability.

To avoid costly system redesigns and maximize engineering reuse for future generations, a modular system design approach is essential. Utilizing System-on-Modules (SoMs) not only reduces hardware complexity but also simplifies the development toolchain. The primary advantage lies in scalability: the ability to precisely adapt computing resources to the task at hand. By adopting a SoM-based strategy, engineers and program managers can increase efficiency and accelerate time-to-market, even when working with limited development resources.

15.30 – 15.50

Low-cost PCB Design with AMD 0.5mm Pitch Package

AMD
Bryan Fletcher, Product Marketing Manager

Extremely small, “super-fine” 0.5mm pitch packages are indispensable in space-constrained applications. AMD super-fine-pitch UltraScale+™ devices also offer a cost advantage. However, traditional PCB design with a super-fine-pitch package can be time-consuming and require more expensive techniques and materials. In this talk, AMD will provide details on a PCB design technique that accommodates 0.5mm pitch packages while still using low-cost FR4 and through-hole vias. This allows for overall system savings with the more affordable 0.5mm pitch package while not increasing the PCB cost.

Get the Right FPGA Quality Through Efficient Requirements Tracking

EmLogic
Espen Tallaksen, CEO

Requirements Tracking (aka Specification Coverage) is getting more and more attention, and is critical for safety (e.g. DO-254) and mission critical (e.g. ESA space and Avionics) applications.

Unfortunately, this is often handled manually, which is very time-consuming and error-prone. UVVM’s Specification coverage allows really efficient requirements tracking, and it generates the reports you need for both mission-critical and safety projects, and in fact for any Project where quality is important.

This presentation gives a brief overview of Specification Coverage before going into more details on proper Requirements Tracking. It also shows what is provided with UVVM and how this could be Applied in a simple way to your testbenches.

UVVM is free and Open Source, and so are all the interface models, randomisation, functional coverage and specification coverage.

16.00 – 16.30

Some don't like it hot - Hotspot Design and Analysis on Datacenter FPGAs

Heidelberg University
Dirk Koch, Professor for Novel Computing Technologies

Usually, we aim for low-power FPGA designs. In this talk, we ask the question the other way round: how much power can an FPGA possibly burn – and, most importantly: can we damage or age an FPGA or otherwise harm the integrity of a corresponding system? The talk will provide a small overview on real-world attacks and details our experiences of successfully planting a simple denial-of-service attack on a major FPGA cloud provider. As a more subtle attack, we also created hotspot designs that concentrate over 100 W power consumption in just 1% of the FPGA area to create substantial local aging.

Key takeaways from this talk will include an understanding of power-induced security threats and how to design more secure and robust FPGA systems.

16.30 – close