London 26 speakers

Ansgar Hein is Chairman of the Board at the Standardization Group for Embedded Technologies (SGET). With more than 25 years of experience spanning technology, strategic business development, and international marketing, he combines technical understanding with a strong focus on ecosystem building and industry collaboration. As a frequent speaker and moderator, Ansgar is known for translating complex technical topics into practical and engaging insights.

Building an Open FPGA Module Standard: Lessons Learned, Trade-offs, and Real-World Design Decisions

FPGA projects rarely fail because of logic design. They fail because everything around the FPGA has to be rebuilt, again and again.

Form factors, pinouts, thermal concepts, and carrier board architectures are typically defined from scratch for each project. This leads to long development cycles, limited reuse, and tightly coupled vendor ecosystems.

While modular approaches are well established in CPU-based systems, applying the same principles to FPGA designs turns out to be significantly more complex.

This talk explores what it takes to move from one-off FPGA designs to modular, reusable system architectures, based on the development of the Open Harmonized FPGA Module (oHFM).

Instead of presenting the standard itself, the focus is on the engineering decisions behind it:

• Why FPGA modularization is fundamentally harder than CPU-based COM approaches
• How different integration models lead to conflicting requirements
• Signal grouping, scalability, and system-level constraints
• Mechanical, thermal, and high-speed interface trade-offs
• What worked, what didn’t, and where compromises were necessary

One key outcome was the realization that a single module concept cannot cover the full range of FPGA use cases, leading to two distinct integration approaches with different constraints and trade-offs.

Attendees will gain a practical understanding of how to approach modular FPGA system design, what pitfalls to avoid, and how to make better architectural decisions when designing scalable FPGA-based products.

Dr. Baha Hashimi is an Embedded Systems Specialist at Avnet Silica. He has experience in developing communication system models, developing DSP Algorithms and implementation on DSP devices, and developing real time embedded software on micro processors/DSP devices.

AMD Versal AI Engine Architecture and DSP Application Development Flow

5G wireless communication systems and high resolution medical imaging are compute intensive applications. This session will demonstrate how the intense computation needed for these applications can be accelerated using the AI Engines in Versal to perform DSP workloads. This presentation provides an overview of the AI Engine architecture and the development flow for creating efficient DSP applications, covering key aspects such as programming methodology, functional verification and validation using AMD development tools, enabling attendees to understand how they are able to develop DSP for AIE solutions for their own applications.

Bob Storey is CTO of XJTAG. With a degree in electrical and electronic engineering he has spent most of his career writing software, and loves working at the boundary between software and hardware systems. With experience in ethernet networking and security, and the last 20 years spent working at XJTAG, he is passionate about improving best practice across the electronics industry when it comes to bring-up and test of designs in both prototyping and in manufacture.

Making Electronics Under Pressure

Throughout the whole product development lifecycle there is more pressure than ever to move fast and do it right first time. With new PCB technologies such as High-Density Interconnect, blind vias and embedded components becoming increasingly common we will discuss test methodologies and architectures at both device and board level which can help engineers make the right choice for their needs. There is no golden ticket!

Bryan Fletcher joined AMD in 2022 as a Senior Marketing Manager in the Adaptive and Embedded Computing Group. He started his career working with simple programmable logic devices at Hewlett-Packard, later advancing to the original Virtex™ family while supporting Evans & Sutherland flight simulators. Fletcher then brought his passion for programmable logic to Avnet, where he worked as an FAE, technical marketer, and trainer. During his time there, he helped develop more than 30 FPGA and SoC evaluation boards, including the low-cost Spartan 2 Evaluation Board, Spartan 6 LX9 MicroBoard, ZedBoard, Ultra96-V2, and ZUBoard-1CG. He holds a Master of Science degree in Electrical Engineering from Utah State University.

Low-cost PCB Design with AMD 0.5mm Pitch Package

Extremely small, “super-fine” 0.5mm pitch packages are indispensable in space-constrained applications. AMD super-fine-pitch UltraScale+™ devices also offer a cost advantage. However, traditional PCB design with a super-fine-pitch package can be time-consuming and require more expensive techniques and materials. In this talk, AMD will provide details on a PCB design technique that accommodates 0.5mm pitch packages while still using low-cost FR4 and through-hole vias. This allows for overall system savings with the more affordable 0.5mm pitch package while not increasing the PCB cost.

Craig Petrie is Vice President at Molex. Craig is a leading industry figure with 24 years of experience in all aspects of FPGA and RFSoC technology. Craig started his career programming FPGAs before moving into Field Applications Engineering where he worked with key customers to help their projects succeed. His role continued to expand to include product strategy and responsibility for all aspects of product specification and development. Craig holds a Masters Degree in Engineering from The University of Strathclyde, Scotland. Based in the UK, Craig travels frequently to the US and Europe to work directly with key customers and partners.

RFSoC at the Edge

Molex uses FPGA and RFSoC devices, tools and IP to help customers solve a variety of challenging application requirements. In this presentation, Molex will provide insight into how customers are using FPGA technology within complex systems at the edge and within the data centres to meet the needs of emerging compute, network, storage and sensor processing workloads.

Denis is hands-on technical contributor with a Software Engineering background. His experience spans embedded development, FPGA design, compiler development, and AI model optimization/modification.

Bringing Software’s Proven Lessons to Modern FPGA Application Design

Have you ever wondered whether applications really need a processor? Is firmware, an operating system, and a driver stack always required – or is that simply how we learned to structure systems?

What if application logic could be implemented directly on an FPGA, with the same level of structure and clarity we expect from software development, but without firmware overhead, operating systems, or CPUs? Livt challenges this long-standing assumption by enabling complete applications to be built directly in hardware. A processor becomes an optional integration choice rather than a prerequisite, enabling simpler systems, lower latency, and more deterministic behavior – while retaining application-level structure.

In software development, engineers rarely work at the processor or assembler level, reinventing basic functionality for every project. Progress became possible because higher-level abstractions, shared libraries, frameworks, and reusable building blocks emerged. FPGA development, by contrast, is still largely performed at a low level. Many teams maintain their own sets of abstractions, engineers repeatedly solve the same problems, and designs quickly hit a wall of complexity as systems grow.

Livt addresses this by making application development on FPGAs possible. It is built around hardware-native semantics – explicit state machines, multiplexing, and concurrency – which map directly to HDL, while enabling reuse at multiple layers. Language constructs support encapsulation, interfaces, and composition. On top of that, developers work with packages and frameworks instead of large, monolithic IP blocks. These layers can be stacked, reused, and evolved, allowing functionality to grow incrementally rather than exponentially in complexity – and providing the structure required for modern, tool-assisted and guided development workflows.

Livt invites engineers to rethink FPGA design as true application development in hardware – enabling complex, structured systems to be built directly on silicon, with or without a processor.

During the session, you will see an example application of a secure webservice – no OS, no CPU, no attacks. Livt!

His main research interests include run-time reconfigurable systems based on FPGAs, embedded systems, computer architecture, VLSI design, and hardware security. Dirk’s group developed the GoAhead tool for implementing partial reconfiguration on FPGAs, the FPGADefender bitstream virus scanner, and the FABulous open-source embedded FPGA generation framework which has been used in over 30 manufactured chips. Dirk Koch is the author of the book “Partial Reconfiguration on FPGAs” and a co-editor of the book “FPGAs for Software Programmers”.

Some don’t like It hot – Hotspot Design and Analysis on Datacenter FPGAs

Usually, we aim for low-power FPGA designs. In this talk, we ask the question the other way round: how much power can an FPGA possibly burn – and, most importantly: can we damage or age an FPGA or otherwise harm the integrity of a corresponding system? The talk will provide a small overview on real-world attacks and details our experiences of successfully planting a simple denial-of-service attack on a major FPGA cloud provider. As a more subtle attack, we also created hotspot designs that concentrate over 100 W power consumption in just 1% of the FPGA area to create substantial local aging.

Key takeaways from this talk will include an understanding of power-induced security threats and how to design more secure and robust FPGA systems.

Espen Tallaksen is the CEO of EmLogic, in Norway, as well as the author and architect of the Open Source UVVM (Universal VHDL Verification Methodology).

He has a strong interest in methodology cultivation and pragmatic efficiency and quality improvement, and he has given lots of technical presentations at various international conferences with great feedback. He also gives courses on FPGA Design and Verification world-wide.

Get the Right FPGA Quality Through Efficient Requirements Tracking

Requirements Tracking (aka Specification Coverage) is getting more and more attention, and is critical for safety (e.g. DO-254) and mission critical (e.g. ESA space and Avionics) applications.

Unfortunately, this is often handled manually, which is very time-consuming and error-prone. UVVM’s Specification coverage allows really efficient requirements tracking, and it generates the reports you need for both mission-critical and safety projects, and in fact for any Project where quality is important.

This presentation gives a brief overview of Specification Coverage before going into more details on proper Requirements Tracking. It also shows what is provided with UVVM and how this could be Applied in a simple way to your testbenches.

UVVM is free and Open Source, and so are all the interface models, randomisation, functional coverage and specification coverage.

Before establishing Exostiv Labs, Frederic worked as a designer and provider of design services for companies such as Barco, NXP, Philips, Atos, and ASML. This experience spanned various industries using semiconductors, including finance, medical imaging, video and broadcast, military, and avionics. With over 20 years of expertise, Frederic and his co-founders envisioned Exostiv Labs with the belief that properly instrumented FPGAs are crucial for enhancing product quality and streamlining design cycles.

Beyond the Lab Bench: Boosting FPGA Development Productivity with Remote & Hybrid FPGA prototyping

For many companies, limited access to high-end FPGA boards, long compile times, and the physical constraints of lab-based debugging create a significant ‘hardware bottleneck’ – particularly early in the design cycle. This session challenges the traditional ‘one-engineer, one-board’ model by exploring the shift toward Remote and Hybrid FPGA Prototyping.

To succeed, such a model must bridge the ‘visibility gap’ inherent to off-site hardware. This requires delivering lab-quality signal tracing and stimulus generation through an intuitive interface that integrates into the engineer’s verification and validation workflow. During this session, the audience will learn about Exostiv Labs’ current experimentation in building a remote and hybrid prototyping proposition specifically designed to meet the needs of the FPGA engineering community

Graham is a technology enthusiast who has worked with FPGAs throughout his career. Over 25 years at Altera, he has supported customers worldwide as a Field Applications Engineer, led FAE teams, and mentored fellow engineers. He has partnered with organizations ranging from startups to established industry leaders, enabling new products and capabilities across a wide range of applications. Having witnessed many advancements in FPGA technology, Graham is excited about the future of Altera FPGAs.

FPGA Security demystified

With the emergence of the Cyber Resilience Act and other industry inflection points, design security is becoming more important and certainly more talked about. But what is design security, what features are available in FPGAs and how do they help secure my design and my product?

During this talk, we will explore the fundamentals of design security, examine how security features have evolved, and discuss how Altera is prepared for a post-quantum world. We will review specific FPGA security features, the threats they mitigate, and how they are implemented, so that security becomes less of a mystery and more of routine aspect of FPGA engineering.

Harald is an FPGA veteran with more than 30 years of FPGA experience. He studied communications engineering at the FH Koblenz (Dipl-Ing(FH)). He started his professional career in 1987 at Siemens AG in Munich, then moved to CAE vendor Viewlogic Systems in 1992 in a technical sales position and started in the FPGA world at Actel in 1995. After Actel, he moved to Lattice Semiconductor in 2000, where he held a technical and sales management position. Since 2020 he built up the Efinix organization in EMEA and is now VP Sales EMEA and Managing Director EMEA.

Leading Low Power, High Speed Small Form Factor System Devices

Efinix offers FPGAs in a small form factor that can serve as system controllers, ideally suited for demanding edge applications. The new System in Package (SiP) devices further simplify integration by combining multiple advantages such as lower power consumption, a smaller footprint, and easier PCB integration. Examples include the Ti125 SIP with integrated HyperRAM and the Ti135 SIP with integrated LPDDR4. These devices deliver unprecedented performance in terms of speed and power efficiency. This presentation provides a detailed overview of the new devices and their features, along with exemplary applications.

Efinity Flow with RISC-V: Program and Debug on the Eval Board

This hands-on workshop guides participants through the complete FPGA development flow using the Efinity toolchain, with a focus on integrating and debugging a RISC-V soft processor on an evaluation board. Attendees will begin by setting up a project, adding the necessary design files and IP, and configuring I/O using the Interface Designer. The session also covers applying timing constraints with SDC files, generating a bitstream, and programming the evaluation board.

Building on this foundation, the workshop explores practical debugging techniques using JTAG, JTAG Bridge, and built-in tools such as the Debugger and VIO. Participants will learn how to insert debug logic, define trigger conditions, and monitor or control signals in real time.

The second half of the session introduces the Efinity RISC-V IDE, where attendees will open, build, and run an example project on hardware, as well as explore software debugging on the RISC-V core. By the end of the workshop, participants will have gained a clear understanding of the Efinity workflow and how to effectively develop and debug both FPGA designs and embedded RISC-V applications. Attendees will be able to keep the boards for future engineering.

Prerequisites: Attendees should have a basic understanding of FPGA design flows, and should arrive equipped with a laptop running Windows 11 or Ubuntu 20.04, and a USB-A hub to connect the evaluation board. Laptops should also have Efinity 2026.1 with latest patch and Efinity RISC-V 2026.1 installed.

Ian Pearson is a Principal Field Applications Engineer with Microchip Technology covering FPGA, security and IoT. He is a technical lead on the Cyber Resilience Act (CRA) and oversees threat modelling, Threat Analysis and Risk Assessment (TARA) and CRA compliance processes. He also serves as the chair of the IoT Security Foundation’s Security Assurance Framework Working Group, which is responsible for providing best practice guidance on the development of secure products.

The Cyber Resilience Act Is Here: Are Your FPGAs Ready?

This presentation explores the EU Cyber Resilience Act (CRA) and its far-reaching impact on connected products entering the European market. It explains the CRA’s essential requirements, life cycle based security expectations, and mandatory vulnerability management processes. The session outlines risk-based product classifications, documentation and reporting obligations, and the role of emerging horizontal and vertical standards in demonstrating compliance. It also clarifies the responsibilities for manufacturers, including support and security update requirements, and highlights how the CRA applies to both new and legacy products. Pearson will also outline how Microchip Technology is setting the benchmark for secure FPGA design, supporting customers with robust security architectures, comprehensive documentation, and proven, security-focused components— enabling faster, more confident compliance with the CRA.

Jack Sampford is Chief Firmware Engineer at Phixos, with experience leading the design and implementation of multiple FPGA-based products, primarily for high integrity applications. Jack has worked with Phixos for the past 5 years providing engineering services to many industry-leading OEMs, particularly in the domain of mission- and safety-critical FPGA designs.

Designing and Verifying FPGAs for Spaceflight Applications

FPGAs are used for a multitude of purposes in spaceflight applications such as image processing, spacecraft control, and communications. They are commonly used in both low earth orbit (LEO) and geostationary orbit (GEO) satellites, with each presenting a unique operational environment and lifespan considerations. This technical session focuses particularly on the challenges faced when designing and implementing FPGAs for geostationary satellites including extreme temperatures, technology limitations, and radiation effects. It also covers the mitigations which can be put in place to account for these challenges, and the verification and validation techniques which can be used to give confidence in these mitigations.

Kevin Roth is a senior leader at Alpha Data, serving as Product Director where he plays a central role in shaping the company’s advanced FPGA‑based and high‑performance computing product lines. With a strong technical foundation and a reputation for hands‑on leadership, Kevin Roth drives product strategy, cross‑functional execution, and customer engagement across demanding application domains environments including aerospace, defence, datacentre, and space.

A Modular Solution for Versal RF Deployment

In this talk, Alpha Data will present the modular approach taken to solve the difficulties in delivering Versal RF technology based systems into development and deployable applications. At the core of the approach is the use of a system on module, to allow an economic deployment in a variety of form factors. Digital carrier base boards provide power and digital connection in industry standard form factors. The variety of analogue requirements is handled separately on a different daughter boards to maximize flexibility and standardization of modules. To successfully design, reliable products with such high fidelity analogue performance requires extensive simulation as well as physical prototyping and testing. The highlights of this design process will be presented. The product is not the hardware alone, and highlights of the software development process used to develop the supporting FPGA firmware, IP examples, and development kit will also be presented.

System-Level Design meets AI-Driven Workflows in Modern FPGA Embedded Systems

Designing embedded applications demands an evolving system-level perspective, where workloads are aligned to the right compute architecture and design flows are optimized for faster, higher-quality implementation. This keynote takes a top-down view of modern design, spanning FPGA flexibility, embedded processing, and heterogeneous compute, while examining how advances in AI-driven tools are reshaping FPGA workflows through co-pilot-style interaction for design and verification. Together, these trends are enabling architects and FPGA designers to move from concept to implementation with greater speed and confidence. This session will explore what that means in practice.

Matt is a highly technical field applications engineer with over 20 years experience as a customer facing FPGA and ASIC engineer. He is principally hardware based but has considerable software experience and regularly draws upon both to achieve technical closure. Matt has extensive experience with all aspects of FPGA design from system architecture through RTL design, Timing Closure, System and Floor Planning, and verification through hardware and logic simulation. He is also familiar with embedded processor design, software coding and debug.

Practical security fundamentals for FPGA Engineers

Security is increasingly becoming a core design requirement, even for engineers who do not specialize in it. This session introduces the essential security concepts; trust, privacy, integrity, and availability, in a way that connects directly to FPGA development and real‑world system architecture. Instead of focusing on cryptography or abstract theory, we look at how these principles influence system design and device selection. Attendees will gain a practical understanding of how security requirements will impact their own designs and how hardware‑based security can significantly strengthen the resilience of FPGA‑centric systems.

Lattice Nexus FPGA Hands-On Workshop

Lattice Semiconductor is proud to host an in-person workshop covering our low-density Nexus range of FPGAs. In this session, we will discuss SW tools, IPs and Development Kits that provide you with a game-changing experience for embedded applications in a wide range of market segments.

Matthew Fransham is a Lead Solutions Architect at Fidus Systems with over 15 years of experience designing and architecting complex embedded systems. At Fidus, he provides system-level technical leadership for high-performance FPGA- and SoC-based platforms, partnering with customers to define robust, timing-critical, and low-latency system architectures.

His background spans FPGA-based systems, processor-centric designs, clocking and synchronization, and complex hardware–software integration. Matthew is known for applying a practical, systems-driven approach to reducing technical risk and guiding teams toward first-time-right execution on high-complexity programs.

He holds an engineering degree and brings deep hands-on experience across the full embedded system design lifecycle.

Learn about IEEE 1588/PTP timing synchronization and distribution within FPGAs, SoCs, and RFSoCs

In this talk, Fidus dives into a compelling discussion on implementing time synchronization and clock distribution in today’s time-reliant embedded systems. They will discuss IEEE 1588/PTP implementations and how the functionality is commonly enabled either solely within, or jointly between, FPGAs, processors, and/or dedicated timing silicon. They’ll share experience of using the locked, recovered clock to generate synchronized sampling clocks for both onboard and multi-board RF/analog frontends (i.e., ADCs and DACs).

Michael Hutchison, Senior Director at AMD, is an industry veteran with more than 20 years of experience architecting, developing, and building leading-edge FPGA and Adaptive SoC products for markets including automotive, consumer, and test & measurement. Michael leads the Customer eXperience Engineering, Software, and Solutions teams. This role encompasses driving the AMD Vivado™, Vitis™, Embedded AI/ML, Embedded System Software, and IP solutions to meet customers’ needs for all AMD embedded products. He is responsible for ensuring that AMD FPGA, Adaptive SoC, and embedded x86 products have a full solution stack available to enable customers in today’s complex development environments. Michael holds a Bachelor of Applied Science in Computer Engineering from Simon Fraser University, holds seven patents, and has lived and worked in Germany and Canada throughout his career.

Agentic AI Workflows for Modern Adaptive SoC Development

Agentic AI is transforming how FPGA developers design, verify, and bring up systems. This hands-on workshop introduces a natural‑language-driven workflow where attendees guide an AI agent through FPGA development, from interpreting design intent to generating hardware and software artifacts. Using intuitive prompts, workshop participants will observe the agent create and integrate AMD Vivado™ block‑design components, configure subsystems, run build flows, and deploy to the AMD FPGA/adaptive SoC hardware platform. The session highlights a modern, software-centric approach to FPGA development, demonstrating how Agentic AI accelerates iteration, reduces complexity, and enables a full concept-to-hardware experience accessible to engineers of all backgrounds.

Nick Theisejans is a hardware and embedded security expert who leads high-security hardware evaluations within the EUCC scheme at TÜV Informationstechnik GmbH. Holding an M. Sc. in IT-Security from Ruhr-University Bochum, he combines a strong academic foundation in theoretical security with over seven years of hands-on experience in the hardware security sector.

From Concept to Certification: Design Paradigms and Countermeasures for Secure FPGA Systems

As FPGAs increasingly become the backbone of space, aerospace, military, and mission-critical applications, new regulatory frameworks strictly demand verified, hardware-level security. However, FPGAs are historically difficult to certify. The main problem is that traditional certification approaches often rely on attacker models assuming physical inaccessibility to the FPGA i.e., the classic Hardware Security Module (HSM) approach. This assumption completely fails in modern edge and field deployments. Drawing on practical insights from an independent security evaluation laboratory, this talk explores the concrete system-engineering challenges of bridging this certification gap and making an FPGA system truly certifiable without assumptions on the environment.

Moving beyond theoretical vulnerabilities, we will detail the demands placed on hardware architects and what core security functionalities – such as secure boot, rollback protection, random number generation and cryptographic primitives – an FPGA architecture must inherently provide to be certifiable. The presentation will provide a twofold breakdown: Logical exploits on the architectural level versus physical threats like side-channel analysis and fault injection. Using architectural block diagrams and system-level concepts, we will dive into how to design effective countermeasures that can withstand these specific real-world attacks. Finally, we will highlight the critical role of a secure supply chain, illustrating why even the most resilient on-chip architecture fails without secure production and provisioning lifecycles.

Ultimately, hardware architects and system engineers will leave with a clear roadmap of evolving security requirements, gaining actionable insights into designing and implementing a certifiable FPGA architecture.

Roland Paul completed his Master’s in Electrical Engineering at ETH Zurich in 1997 and has been working with FPGAs ever since. He began his career as a VHDL developer before moving into hardware/software and system design for distributed High-Performance Computing (HPC) clusters for major companies such as Hewlett Packard.

Roland has been with Enclustra GmbH in Zurich for over 10 years. After starting as the HW Development Manager, he served as VP of Sales for six years, where he focused on developing key accounts and introducing FPGA-based System-on-Modules (SoMs) to development teams worldwide. He is passionate about helping customers optimize system designs to maximize the benefits of edge computing technology.

Future-Proofing the Edge: Strategies for Scalable System Design

Today’s edge computing applications require diverse architectures to balance performance, power consumption, and cost. Modern FPGA-based technologies, such as AMD Versal™ AI Edge Gen2, offer a heterogeneous mix of engines – including scalar processors (Arm cores), video processors (ISP/VCU), AI accelerators (ML/Tensor cores), and adaptable logic. However, since few applications require every feature, and requirements often evolve throughout a product’s lifecycle, a rigid design can be a liability.

To avoid costly system redesigns and maximize engineering reuse for future generations, a modular system design approach is essential. Utilizing System-on-Modules (SoMs) not only reduces hardware complexity but also simplifies the development toolchain. The primary advantage lies in scalability: the ability to precisely adapt computing resources to the task at hand. By adopting a SoM-based strategy, engineers and program managers can increase efficiency and accelerate time-to-market, even when working with limited development resources.

Valtteri is a Field Application Engineer with an education and a background in electrical engineering. Valtteri is a developer expert in FPGA, digital design and hardware. He holds a master degree in electrical engineering at Aalto University and worked previously as a Senior Digital Design Engineer at Xiphera, implementing security solutions and cryptographic algorithms into FPGA systems.

Common Framework for FPGA-based Hardware Root of Trust

A hardware root-of-trust (HW-RoT) is an essential component for establishing and maintaining digital trust on a computing platform. Solutions offering a range of HW-RoT services for a host system include TPM (Trusted Platform Modules), DICE (Device Identification Composition Engine), and open source implementations such as OpenTitan and Caliptra. Verification and validation of these may prove challenging, especially when applied in high-security assurance scenarios. In this presentation we establish a base for essential HW-RoT functions and requirements, and propose a foundation and architecture for building an FPGA-based Root-of-Trust for enhanced security, lower power consumption, crypto agility, as well as streamlined testing and validation.