Objective
In this Lab Note we explore how to power-on an FPGA board safely and predictably. The emphasis is on the practical steps involved in early validation. That means analyzing failure modes, confirming margins, checking component stress, preparing rails, and activating subsystems in a controlled sequence.
By the end, you’ll have a clear, structured approach for powering and debugging new FPGA hardware. All of which reduces risk, accelerates validation, and helps to ensure the board behaves as intended in real-world conditions.
Context
The initial power on of a new FPGA board is an important stage in a hardware project. It’s the point where design assumptions finally meet reality. It’s also the point where latent electrical, mechanical, thermal, or system-level architectural issues emerge. A structured process reduces the risk of damaging components, accelerates debug, and provides confidence the design will behave as intended.
This Lab Note presents a disciplined approach, using three complementary engineering analyses: Failure Mode, Effects, and Criticality Analysis (FMECA); Worst Case Analysis (WCA); and Part Stress Analysis (PSA). Together, these techniques allow engineers to anticipate failures, validate design margins, and ensure that no component is overstressed.
These analyses also highlight issues that extend beyond pure electrical behavior, including analog stability, thermal dissipation, mechanical stress, and fault containment. By identifying single points of failure, verifying that circuits remain functional under extreme tolerances, and ensuring that components operate well within derated limits, you can prevent cascading faults and maintain long-term reliability.
The result is a predictable, safe, and repeatable process that transforms first power on from an uncertain exercise into a managed engineering activity with predictable outcomes.
Overview
To avoid surprises, the power-on process starts well before power is applied. Prior to any analysis taking place, the design’s assumptions and ground rules must be confirmed in terms of what constitutes a failure, what operating limits are expected, and which conditions the system must tolerate. This ensures the board is evaluated consistently, and that early life failures are understood in context. The step-by-step workflow is:
- Confirm design phase analyses — ensure the board has passed FMECA, WCA and PSA before power is applied.
- Prepare for first power on — ensure supplies are current‑limited, loads are isolated, rails are instrumented, and reset/protection circuits are confirmed.
- Apply power incrementally — observe behavior, verify rails, monitor thermal conditions, and check for oscillations or unexpected current draw.
- Activate subsystems one at a time — clocks, I/O, memory, and peripherals, validating each before enabling the next.
- Verify behavior — confirm that real world operation matches analytical predictions and update the analyses based on observed results.
Key concepts
Prior to first power=on, the design phase analyses establish that its behavior under real electrical, thermal and mechanical conditions is already understood. Each one builds on the next with PSA, for example, working out the stresses on components. WCA then ensures that, with aging, tolerances, and drift, the circuits still function as required. Finally, FMECA ensures that should a component fail we are able to detect and isolate the fault, and determine the failure rate taking into account the PSA.
Part Stress Analysis (PSA)
PSA checks that no component is overstressed under worst case operating conditions. Components must operate well within their derated limits to avoid immediate failure and to ensure long term reliability. Derating rules, such as those defined in ECSS Q ST 30 11C, specify allowable fractions of rated voltage, current, power, and junction temperature for capacitors, resistors, diodes, connectors, and logic ICs.
PSA compares each component’s rating with its worst case operating conditions to determine whether it passes or fails. Examples include checking that capacitors operate below 60% of their rated voltage, resistors dissipate less than half their rated power, and semiconductors remain within safe junction temperatures.
Worst Case Analysis (WCA)
WCA ensures that the design functions correctly across the full range of component tolerances, environmental conditions, and aging effects. Because no component value is exact, WCA evaluates whether circuits continue to operate under extreme combinations of resistor, capacitor, inductor, logic level, and power supply variations.
The analysis covers analog stability, including gain and phase margins. It also examines timing behavior such as clocks, timeouts, and buffer fill/empty conditions, along with power supply characteristics like voltage limits, current protection, and transient response. Thermal analysis then identifies major heat sources, estimates dissipation, and considers placement for airflow or conduction.
Failure Mode, Effects, and Criticality Analysis (FMECA)
FMECA is a systematic process which identifies how components or subsystems can fail and how those failures affect system behavior. It starts with clear ground rules, typically assuming one failure at a time, and evaluates severity, likelihood, visibility, and containment.
Some failures show up clearly through status reporting or abnormal behavior. Others, however, are silent. A design must also account for false positives, where a fault is indicated but none exists; and false negatives, where a real fault produces no observable effect. These distinctions shape how faults are classified and how monitoring and containment strategies are defined. Containment prevents propagation, for example by separating redundant paths, isolating I/O banks, or adding over voltage protection or shutdown mechanisms.
FMECA also examines how far a fault can propagate, from local effects to system level cascades, guiding decisions on where isolation, redundancy, or protective circuitry is required. It highlights single points of failure and informs early architectural choices, incorporating an understanding of early life, useful life, and wear out behavior, shown by the “bathtub curve.”
Figure 1: The bathtub curve, showing the typical failure rate of FPGAs over their lifecycle
Other Failure Modes
A structured power-on process also considers failures beyond electrical behavior. In some designs, analog feedback loops become unstable, which is why gain and phase margin analysis matters. Depending on the environment, thermal expansion or vibration may force the use of flexible connections or different package types. These factors influence both WCA and PSA and must be accounted for before first power on.
Design trade-offs
Every FPGA design involves trade-offs. It’s the classic balancing act where there is a choice between reliability, cost, and complexity and you can only choose two of the options. Conservative derating improves long‑term reliability but comes with the downside that it may require larger or more expensive components. Compare this with redundancy and containment strategies such as separating nominal and redundant buffers, adding shutdown or crowbar circuits, or isolating I/O banks. This will improve fault tolerance but increase board area, power consumption, and design effort.
There are trade-offs in FMECA as well, especially around assumptions and visibility. It typically assumes only one failure at a time and can be optimistic if failure visibility is poor or if architectural assumptions are incomplete. Reliability predictions like Failures In Time (FIT) and Mean Time Between Failures (MTBF) are useful, but they only apply to large populations of components or a system where the FIT and its inverse the MTBF are an output of the FMECA. They don’t tell you when a specific device or system will fail, but it can be used to determine the probability of success for a system with a given FIT / MTBF being operational over the required time. They also exclude early life and wear out behavior. These limitations mean that analytical reliability figures must be interpreted cautiously when assessing real world risk. Adding mechanisms to detect or contain faults increases robustness but may complicate the design.
WCA introduces further considerations. Designing for worst‑case tolerances, temperature extremes, aging, and supply variation may require wider margins, more robust regulators, or additional filtering. Analog stability may require gain and phase‑margin analysis, test points, or component changes. Thermal analysis may influence component placement or require improved airflow or conduction paths.
Implementation
Before a new FPGA board is powered for the first time, the design should already have passed the PSA, WCA and FMECA analyses. These are performed prior to PCB fabrication and assembly, and ensure the hardware is safe to power-on and behaves predictably under real world conditions.
The failure mode review, for example, will identify how components or subsystems could fail, how those failures would appear, and whether any single points of failure require architectural mitigation. The worst-case tolerance analysis will validate that circuits continue to operate across component tolerances, temperature extremes, supply variation, aging effects, and analog stability limits. The part stress validation will then confirm that no component is overstressed under worst-case conditions and that all operate comfortably within derated limits.
The structured power-on process then involves the following stages.
Prepare for first power on
Once the analyses are complete, the board is finally ready for its first controlled power-up. This stage focuses on minimizing risk and ensuring that the testbench is prepared to catch issues early.
- Check the pin 1 indicators are correct and follow the assembly diagram
- Measure the impedance on an unpowered board between the voltage rails and ground to ensure there are no shorts
- Set current limits on the bench supply
- Verify pull ups, pull downs and reset circuits
- Confirm power supply sequencing and protection mechanisms
- Prepare thermal monitoring (thermal camera or IR thermometer)
Apply power incrementally
Now apply power gradually. This lets you observe behavior and stop immediately if anything looks wrong.
- Begin with current‑limited power and reduce voltage on rails that safely tolerate undervoltage.
- Observe rail behavior for overshoot, oscillation, or instability
- Increase to nominal levels only when stable
- Verify regulator outputs
- Check for unexpected current draw
- Monitor for thermal hotspots
- Confirm no unexpected resets
Activate subsystems one at a time
After the power rails stabilize, the subsystems can be brought online one at a time, so that the bring up happens step by step, in a methodical way. This isolates issues and ensures that each block behaves correctly before the next is introduced.
- Bring up clocks and verify stability
- Bring up memory interfaces
- Enable I/O interfaces and peripherals incrementally, verifying predictable behavior
- Validate analog circuits (no oscillation)
- Confirm that any redundant paths operate independently
Document findings
The final stage is the inevitable but necessary documentation. Capture what happened, compare it with the analyses, and update the records accordingly. This closes the loop between prediction and observation.
- Capture waveforms, voltages and thermal images
- Record anomalies and unexpected behavior
- Confirm expected behavior matches FMECA, WCA and PSA predictions
- Update analyses to reflect real world results
- Note any early life failures or deviations from expected reliability
Verification
Verification checks that the board behaves as predicted by the analyses. It also ensures that no unexpected failure modes appear during power-on. Voltage rails must remain within tolerance under varying load and supply conditions, and power supply protection mechanisms such as current limits, shutdown paths and crowbar circuits must operate correctly. Thermal behavior should remain within the limits predicted by WCA, with no component exceeding its derated temperature or dissipating more power than predicted.
Analog and timing circuits must be checked for stability, ensuring that feedback loops do not oscillate and that clocks, timeouts and buffer behavior remain within expected bounds. Mechanical considerations such as thermal expansion or vibration sensitivity may also need to be observed during early testing.
Verification must also confirm the assumptions made during FMECA. Failures should be visible where expected, silent failures should not occur, and containment mechanisms must prevent faults from propagating. Redundant paths should operate independently, and single points of failure should behave as anticipated. Early life failures, predicted by the bathtub curve, should not appear during initial operation.
As subsystems are activated incrementally, each must be validated against analytical predictions. Rails, clocks, I/O, memory and peripherals should behave predictably, with no unexpected resets, oscillations, or current draw. The combined results provide confidence that the board operates safely within its design margins and that the analyses accurately reflect real world behavior.
Verification checklist
- Rails within tolerance under varying load and supply conditions, with any under load issues discovered early in bring up
- No component exceeds its derated stress or thermal limits
- No unexpected current draw or rail overshoot
- Power supply protection mechanisms (current limit, shutdown, crowbar) operate correctly
- Clocks stable with no jitter, drift, or unexpected resets
- Timing circuits (timeouts, buffers, monostable) behave within expected bounds
- Analog feedback loops remain stable with no oscillation
- I/O behaves predictably, including nominal and redundant paths
- Redundant buffers operate independently and are correctly isolated
- Faults are visible where expected, with no silent or falsely reported failures
- Containment mechanisms prevent fault propagation
- Subsystems activate in sequence without unexpected interactions
- No thermal hotspots, with heat dissipation matching WCA predictions
- Mechanical assumptions hold, with no issues from thermal expansion or vibration
- No early life failures during initial operation and, if there are, an understanding of why
- Real world behavior matches analytical predictions from FMECA, WCA and PSA
Expected output
A successful initial power-on results in a board that powers up safely and behaves consistently with the predictions from FMECA, WCA and PSA. Voltage rails remain within tolerance under varying load and supply conditions, and power supply protection mechanisms such as current limits, shutdown paths and crowbar circuits operate correctly. No component exceeds its derated stress or thermal limits, and thermal behavior matches the expectations from worst case analysis.
In a successful bring-up, analog and timing circuits stay stable without oscillation, resets, or timing issues. Similarly, I/O behaves predictably, redundant paths operate independently, and containment mechanisms prevent faults from propagating. Finally, failures are visible where expected, with no silent or falsely reported faults, and no early life failures appear during initial operation.
Variations
Power-on requirements vary across domains. Space grade and high reliability systems may require conservative derating, extensive redundancy and strict containment strategies, along with detailed thermal and mechanical analysis. Industrial systems may emphasize supply variation tolerance, transient behavior and long term aging effects. Consumer devices may prioritize cost and accept higher component stress or reduced margins.
Use cases differ in their derating policies. Environmental factors such as temperature, vibration, or radiation can call for additional analysis. Mixed signal boards also require particular attention to analog stability and noise coupling, while systems with tight timing constraints may require deeper analysis of clocks, timeouts and buffer behavior. These variations influence the depth of FMECA, WCA and PSA required before first power on.
References
ECSS‑Q‑ST‑30‑11C — Derating rules for space‑grade electrical, electronic, and electromechanical components.
Revision history
August 2026 – v1.0 – Initial release