Objective
In the fourth Lab Note in this series, Understanding ADC performance: The foundations of analog‑to‑ digital conversion, we examine how to test an ADC, generate a single tone with an Analog Discovery 3, capture a contiguous record in an FPGA, and compute SNR, THD, SINAD, SFDR and ENOB from the FFT.
In this Lab Note we turn the problem around and test a DAC. Here, the roles are reversed: the FPGA is now the signal source, generating the test waveform digitally, and the measurement instrument sits on the analog side.
This brings one significant advantage which we do not have in ADC testing. When testing the ADC, the stimulus comes from an external generator where the clock is free-running with respect to the FPGA sampling clock, so true coherent sampling cannot be guaranteed and we have to fall back on windowing.
When testing a DAC, we author the sample data ourselves, so we can construct a waveform which, by definition, is exactly coherent with the sample clock. There is no window, no leakage and no approximation, provided we follow the coherent generation rule, explained in the Key Concepts section.
In this way, it gives us the ability to generate a perfectly coherent stimulus, drive the DAC under controlled conditions, and test its dynamic behavior directly from the resulting spectrum.
Context
The DAC under test in this Lab Note is hosted on an FPGA platform with a SYZYGY-connected DAC module, allowing waveforms to be generated in Python and played out through the FPGA at the sample rate.
Many of the parameters that feature will be familiar from the ADC Lab Note, which you can reference if you need to for a fuller explanation in its Key concepts section.
The static parameters are the offset error, gain error, differential non-linearity and integral non-linearity of the transfer function, measured code by code. The dynamic parameters are the SNR, THD, SFDR and SINAD, measured from the spectrum of a single tone.
For communications applications, the two-tone intermodulation distortion, IMD, is often the more relevant figure, since a transmit DAC rarely carries a single clean sine wave in service.
Key concepts
Settling time and glitch impulse energy
Beyond the typical static and dynamic parameters we use in ADC, two further parameters are specific to DACs. The settling time is the time taken for the output to settle within a specified error band after a code change. The glitch impulse energy characterizes the transient which occurs at major code transitions, classically at the mid-scale carry where every bit of the code changes at once. Glitch energy appears in the spectrum as elevated harmonic content, so a DAC with poor glitch performance is immediately visible in the FFT-derived spectrum.
The DAC output as a staircase
Where a DAC differs fundamentally from an ADC is at its output. The DAC output is not the smooth waveform of our imagination but a staircase, with the output held constant for a full sample period at each code. This zero-order hold has two consequences which every DAC test must account for. First, the held output applies a sinc-shaped amplitude roll-off to the spectrum which reaches -3.92 dB at the Nyquist frequency:
A(f) = sin(pi f / Fs) / (pi f / Fs)
A test tone placed near Nyquist will therefore measure low even from a perfect DAC, and the analysis must either correct for the sinc or keep the test frequencies low enough that the roll-off is negligible.
Images and the Nyquist zone
The sampled nature of the output means images of the wanted tone appear around every multiple of the sample rate, at k x Fs +/- Fout, attenuated only by the same sinc envelope. These images are not distortion and no amount of DAC quality removes them. They are removed by the analog reconstruction filter which follows the DAC.
When measuring the DAC itself we must therefore be clear about whether we are measuring within the first Nyquist zone, where the DAC performance dominates, or across a wider bandwidth where the images and the reconstruction filter dominate.
Coherent waveform generation
The coherent generation rule mentioned in the introduction is where the test waveform is stored in a buffer of N samples and played out in a continuous loop.
For the output to be spectrally pure the waveform must be continuous across the buffer wrap, which means the buffer must contain an exact integer number of cycles, M, of the test tone. If it does, the splice from the last sample back to the first is invisible and the tone lands exactly on FFT bin M with no leakage. If it does not, the periodic discontinuity at the wrap point spreads energy right across the spectrum and ruins the measurement.
As with ADC testing, choosing M to be odd, and ideally mutually prime with N, ensures every sample in the buffer sits at a unique phase of the tone, which decorrelates the quantization error and prevents the quantization energy concentrating into discrete spurs.
Test setup and methodology
Measuring the output
The measurement instrument used for this Lab Note is the Analog Discovery 3, which serves as the receiver for testing the DAC. Its oscilloscope inputs digitize at 14 bits and up to 125 MSPS, a substantial step beyond the 8-bit front-end of a general-purpose scope.
Both the WaveForms application and its SDK expose the capture, and the time domain view confirms the tone exists at the right frequency and amplitude, catches gross faults such as data format errors or a tone placed below the output transformer’s passband, and allows the same records to be pulled into Python for spectral analysis. The limits of the AD3 as a spectral instrument are quantified in the following section, and a laboratory spectrum analyzer remains the reference where the last few dB matter.
Instrument resolution
Before any measurement is made it is worth asking if the test equipment is actually capable of seeing the performance you are trying to measure. Every instrument in the chain has its own resolution and noise floor, and the measured result is always the composite of the device under test and everything used to observe it. The poorer performer dominates, and if that is the instrument rather than the DAC, the measurement characterizes the test bench, not the device.
Bit depth gives a quick way to reason about this. The ideal SNR of an N-bit converter, from the familiar expression, is 6.02N + 1.76 dB. For the 12-bit AD9116 that is 74 dB, and a fair measurement of it needs an instrument with meaningfully more dynamic range. As a rule of thumb, this is 6 dB to 10 dB more, so that the instrument contributes less than a dB of error to the result.
Working through the instruments on this bench makes the point concrete. A general-purpose oscilloscope typically carries an 8-bit ADC, an ideal ceiling of around 50 dB and in practice somewhat less. This is perfect for confirming a waveform exists, its frequency and its amplitude, and entirely incapable of measuring 12-bit distortion or noise performance.
The Analog Discovery 3 used here sits usefully higher, with 14-bit scope inputs whose ideal ceiling of 86 dB comfortably exceeds the DAC’s 74 dB. In practice, its front-end noise and distortion land its usable dynamic range in the region of the DAC’s own performance rather than decisively beyond it, which means the margin rule above is only marginally satisfied. Results measured through the AD3 are therefore honest working figures with a small instrument contribution, and where a headline number approaches the AD3’s own floor it should be quoted as instrument bounded.
The reason the margin matters is that the instrument’s noise and the DAC’s noise add in power in every FFT bin, and the FFT cannot tell which noise it is looking at. If the instrument is the poorer performer by 20 dB, the DAC’s contribution moves the total by less than a tenth of a dB, far below run-to-run repeatability, and the measurement simply reports the instrument.
In that situation, the most a result can honestly say about the DAC is a one-sided bound: the device is no worse than the composite figure. A spectrum analyzer sidesteps the resolution question, since its narrowband architecture routinely offers 80 dB or more of spurious free range, which is why it remains the reference instrument for converter work.
Stimulus resolution
Resolution also matters on the generation side, in a way that is unique to DAC testing. The test waveform is itself quantized to the DAC’s 12 bits before it ever reaches the device, so the stimulus arrives carrying its own quantization noise at the ideal 74 dB level. This is not a defect to be eliminated, it is the very noise floor we are trying to measure, but it does mean the digital waveform must not degrade it further.
Careless generation can degrade it. Scaling the waveform well below full scale throws away resolution, where a tone at -30 dBFS costs us 5 effective bits of raw measurement, and a poorly chosen cycle count can concentrate the quantization error into discrete spurs rather than a smooth floor. This is the deeper reason for the odd-M rule introduced earlier: with an odd cycle count, mutually prime with the buffer length, every sample lands on a unique phase, the quantization error decorrelates from the tone, and its energy spreads evenly across the spectrum. With an even M dividing the buffer length, sample phases repeat, the same rounding errors recur periodically and the error energy piles into harmonically-related spurs which can be mistaken for genuine DAC distortion.
Record length and processing gain
Finally, resolution and record length interact. The FFT processing gain of 10 log10(NFFT / 2) lets a measurement resolve features far below a single LSB of either converter, which is why a 65536 point capture can display a noise floor near -115 dBc from a 14-bit receiver.
Processing gain lowers the floor of the plot, not the integrated noise, so it does not relax the instrument requirement above, but it does mean that with a long enough record even a modest instrument can locate and identify discrete spurs well below its own noise, which is often exactly what a debugging session needs.
The practical summary for this Lab note is honest and simple: the AD3 time domain view confirms existence, frequency and amplitude. The AD3 captures analyzed in Python provide the working dynamic figures with a small and acknowledged instrument contribution, and a laboratory spectrum analyzer remains the reference where the last few dB matter.
FPGA design
The FPGA design has four responsibilities: accept a waveform from the host, store it, play it out to the DAC continuously at the sample rate, and configure the DAC itself. The architecture follows the same philosophy as the ADC capture design, a small number of simple blocks joined by standard interfaces, with all intelligence kept on the host in Python.
Host interface
The host interface uses Opal Kelly FrontPanel, which provides ready-made HDL endpoints connected to the USB 3.0 interface and a matching host API available in Python. A Pipe In endpoint provides the bulk transfer path for downloading waveform data into the buffer.
Wire In endpoints carry the control state: the playback length N, the playback enable, resets and the bit bang signals for the DAC configuration interface. Wire Out endpoints return status such as the buffer write count, allowing the host to confirm a download completed before enabling playback.
This mirrors the role the SPI protocol block plays in the ADC design, but with the considerable convenience of a supported USB 3.0 path and host bindings that keep the entire test flow in Python.
Waveform buffer
The waveform buffer is a true dual-port Block RAM. Port A sits in the FrontPanel host clock domain and is written by the Pipe In endpoint during download. Port B sits in the DAC sample clock domain and is read by a circular address counter which counts from zero to N – 1 and wraps, where N is the programmed playback length rather than the physical depth of the memory.
This programmable length is what allows the host to load an exact integer number of cycles as required by the coherence rule; the physical buffer might be 16384 samples deep while a particular test uses a 12500 sample loop. The dual-port BRAM also performs the clock domain crossing between the USB and sample clock domains cleanly, since the two ports are independent.
The only signals requiring explicit synchronization are the sparse controls such as the playback enable. Each buffer location holds a sample pair, with the I and Q channel samples packed into one word, so that a single read supplies both DACs each sample period.
DAC driver
The DAC driver is where the AD9116’s interface details matter. Although the AD9116 contains two DACs, the pod wires a single 12-bit data bus, DB0 to DB11, shared between the two channels, with the I and Q samples interleaved on the bus and directed to the correct DAC by the data clock.
The driver therefore uses ODDR output registers on each data bit, presenting the I sample on one edge and the Q sample on the other, with the clock forwarded to the pod through an ODDR in the same manner. There is a timing hazard here, however. If the data to clock timing at the DAC is marginal, or the two edges are not cleanly centered, alternate samples are corrupted and the DAC output grows a spur at Fs/2 – Fout.
The output timing must be constrained so that both edges of the forwarded clock arrive centered in their data windows. Using the clock-to-out relationships from the AD9116 data sheet, and an MMCM phase shift on the forwarded clock provides the adjustment if needed.
Clocking and configuration
Clock generation uses an MMCM driven from the carrier oscillator to synthesize the DAC sample clock, which is then forwarded to the pod on the C2P clock connection, from where the pod routes it to the AD9116 CLKIN. Because the waveform is generated inside the FPGA there is only one clock in the entire signal path, which is precisely why the coherence guarantee holds: the sample data and the sample clock can never drift with respect to one another.
Finally, configuration. The AD9116 configuration pins are dual function. In pin mode the device is configured entirely by pin strapping, with the FORMAT pin selecting between twos complement and offset binary data and the CLKMD and PWRDN pins setting the clock and power state. This is the simplest possible bring up and needs no serial interface at all.
In SPI mode the same pins become a serial port, CS, SCLK and SDIO, giving register-level access to the full feature set including fine gain, offset trims and the internal reference options. The design supports both, with the SPI signals driven by FrontPanel wires bit banged from the host, keeping the configuration logic out of the fabric entirely.
The lesson learned here is that the data format the device expects and the format the waveform generator produces must agree, and a mismatch announces itself as violent glitches at every zero crossing. The pod also provides an op amp enable signal which must be asserted to bring the output stages out of power down.
Figure 1: A Vivado block design showing the top‑level integration for a DAC test or signal‑generation path
Hardware setup
The hardware for this Lab Note is the Opal Kelly XEM7320, an Artix-7 based integration module with FrontPanel USB 3.0 connectivity and SYZYGY peripheral ports, fitted with the Opal Kelly SZG-DAC-AD9116 pod. This pod carries the Analog Devices AD9116, a dual 12-bit TxDAC capable of 125 MSPS. The AD9116 sits in the pin-compatible AD9114 to AD9117 family which spans 8 to 14 bits, so the design developed here scales directly across the family. The combination of FrontPanel and SYZYGY makes this an ideal teaching platform: waveforms can be downloaded from a host PC in Python, and the same SYZYGY approach used for ADC testing carries over to the DAC.
One practical note on the pod itself: in its default configuration the SZG-DAC-AD9116 outputs are AC-coupled through transformers to the SMA connectors. This is ideal for spectral testing of tones but means the pod cannot reproduce DC or very low frequencies as shipped, so static INL and DNL testing through the transformer path is not possible. Opal Kelly documents a resistor change which selects a buffered, DC-coupled output stage instead, should static testing be required.
Software workflow
The host software has the three Python responsibilities cleanly separated. A waveform builder constructs the sample table: a single tone with M odd cycles in N samples for the standard dynamic test, two tones for IMD, or an arbitrary table for application waveforms, scaled to the 12-bit range and packed into the buffer word format.
A download and control script uses the FrontPanel Python API to write the table through the Pipe In endpoint, verify the transfer, configure the DAC and enable playback. The analysis closes the Python loop.
A capture script drives the AD3 scope inputs through the WaveForms SDK, records a contiguous block of samples at a known rate and saves it, at which point adc_analysis.py is reused entirely unchanged: the same windowing, the same harmonic folding, the same report.
One caveat carries over with it. The AD3’s sampling clock is free-running with respect to the XEM7320, so although the DAC output is perfectly coherent with its own sample clock, the capture of it is not coherent with the capture clock, and the analysis must window this. Coherence, bin placement and spur identification transfer identically; only the direction of travel has changed.
Results
The single-tone results table and immediate interpretation
All figures below are three-run means, measured on the Analog Discovery 3 and analyzed in Python. The single-tone test used a coherent tone at 1.037598 MHz at -1 dBFS, generated simultaneously on both DAC channels and captured at the transformer coupled SMA outputs.
Figure 2 above shows a single-tone characterization with a Copied tone waveform on both channels; a full Nyquist spectrum showing the image pair about 25 MHz; and the effective number of bits by analysis bandwidth, and the two-tone IMD3 measurement.
The headline finding is that the DAC’s effective resolution depends entirely on the bandwidth over which it is judged. Within a 10 MHz baseband the AD9116 delivers 10.05 and 10.18 effective bits on the two channels, with SFDR above 73 dBc and THD better than -72 dB. Across the full 0 to 50 MHz measurement bandwidth the same captures yield only 7.23 and 7.28 bits, and the difference is caused by a single mechanism: a strong deterministic image pair at 25 MHz +/- fout, measuring approximately -48.7 dBc on channel 1 and -49.0 dBc on channel 2, which dominates both the wideband SINAD and the wideband SFDR of around 49 dBc.
Figure 3: The effective number of bits by analysis bandwidth and channel; the 10 MHz values exclude the 25 MHz image pair.
Which figure is the fair one to quote? Both, with their bandwidths attached. The images are exactly the kind of out-of-band product the reconstruction filter discussed earlier exists to remove, and any real deployment of this DAC with a baseband signal would filter above 10 MHz as a matter of course, making the 10-bit figure the honest description of delivered performance.
Equally, the wideband figure is the honest description of the raw converter output, and quoting the 10 MHz numbers without disclosing the images would flatter the design. The lesson generalizes: an ENOB without a stated bandwidth is not a specification.
Channel matching
The dual-channel measurement also characterizes channel matching, which the single-channel ADC test shown in the ADC Lab Note cannot. With the same tone copied to both channels, channel 2 measures 0.229 dB higher in amplitude, approximately 2.67 percent, with a phase difference of -0.135 degrees. With the channels driven in quadrature the measured separation is -90.126 degrees, a quadrature phase error of just -0.126 degrees. For the communications applications this DAC family targets, where I and Q balance sets image rejection in the analog upconverter, these are encouraging numbers from an entirely uncalibrated signal path.
Two-tone IMD test
The two-tone test placed coherent tones at 1.037598 MHz and 1.159668 MHz at -7 dBFS per tone. The worst third-order intermodulation product measured -58.82 dBc on channel 1 and -59.00 dBc on channel 2, with tone balance within 0.07 dB on both channels, and wideband SFDR of 50.83 and 51.07 dBc again set by the 25 MHz images rather than by intermodulation. The IMD3 figures sit comfortably below the single-tone harmonic distortion, roughly 13 dB above the THD floor when the reduced per-tone level is accounted for, which is the expected relationship for a converter whose nonlinearity is mild and dominated by low order terms.
Set against the ideal, the in-band results read as a healthy converter measured through an honest instrument. The 10 MHz SNR of around 63 dB sits some 11 dB below the 12-bit ideal of 74 dB, a gap shared between the DAC’s own noise, the delivered amplitude relative to full scale, and the AD3’s contribution, which the resolution discussion earlier noted is not negligible at this level.
The distortion side needs no caveats: THD of -72 dB and in-band SFDR above 73 dBc are strong figures for a 12-bit part measured through a transformer on an uncalibrated bench. Addressing the 25 MHz image pair would bring the wideband and baseband figures together, and its investigation is left for future work.
Revision history
August 2026 – v1.0 – Initial release