US East 26 speakers

Adam Taylor is a chartered engineer and fellow of the Institute of Engineering and Technology. Over his multi-decade career, he has had experience within the public and private sector, developing FPGA-based solutions for a range of applications including RADAR, nuclear reactors, satellites, cryptography and image processing.

From Algorithm to Hardware: Applying Model-Based Design to Real-World Designs

Model-Based Design promises faster development, fewer bugs, and smoother hardware integration, but what does that actually look like in practice?

This panel brings together experts from MathWorks and AMD, along with an industry power user to explore how MATLAB®, Simulink™, and AMD Vitis™ Model Composer, along with code generation tools like HDL Coder™ and AMD Vitis™ HLS are being used today to take algorithms from concept to deployed FPGA and adaptive SoC designs. Moderated by Adam Taylor, we’ll discuss where model-based workflows shine, where they still need careful engineering judgment, and how teams are successfully bridging the gap between simulation and hardware reality.

Expect honest insights, practical lessons learned, and a look at what’s coming next.

I Feel the Need for Speed – Recreating the Historic F14 CADC in a FPGA

As a child of the 80s nothing grabbed my imagination like the F14 in Top Gun. What is little known about the F14 is that it contained arguably the world’s first microprocessor, created by Ray Holt and his team at Garret AiResearch, designed in 1968 and shipped in 1971 two years before the Intel 4004.

Due to its military applications this design was secret until 1998. Recently Ray Holt made his logbooks and design notes available. In this session we will look at how we have recreated this microprocessor, in a modern FPGA. We will explore how we used AI to distil the disparate information contained within the notebooks into requirement specifications and verification plans. With a combined requirement set we are then able to create HDL modules, Test Benches, and a simple verification program for the CADC running on a AMD FPGA. If you like fighter jets, computer history and FPGA this is the session for you.

Alex accumulated 28 years of hands-on experience in various aspects of ASIC and FPGA design and verification. In a previous role and as Verification Prime on a multi-million gates project, Alex combined various verification methods including static linting, formal property checking, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. Alex has an M.S. in Electronics, awarded from Technion, Israel Institute of Technology, and his former employers include IBM, Nortel, Ericsson and Synopsys.

Prevent Late-Stage FPGA Failures with Advanced RTL Linting and CDC Analysis

Modern FPGA and SoC FPGA designs push the limits of complexity, performance, and reliability. Undetected RTL coding issues can silently propagate through synthesis and implementation, leading to costly rework, schedule delays, or unexpected failures during hardware bring-up. Identifying these problems early is critical to achieving predictable and reliable FPGA designs.

Advanced RTL linting provides a powerful static analysis approach tailored specifically for FPGA development. By applying hundreds of FPGA-relevant design rules—including vendor-specific synthesizability checks, Clock Domain Crossing (CDC) verification, and reset network integrity analysis—linting exposes bugs, inefficiencies, and design mismatches long before simulation or lab validation.

In this tech talk, we will demonstrate how advanced linting and CDC analysis directly improve FPGA design robustness and development efficiency. Through practical examples, you’ll see how early RTL analysis helps improve code quality, supports design reuse, reduces iteration cycles, and prevents late-stage surprises during synthesis and place-and-route—ultimately accelerating time-to-market while boosting design confidence.

Bassam Mansour is a Senior Technical Marketing Manager at AMD within the Adaptive and Embedded Computing Group, where he drives customer engagement and adoption of next-generation high-speed connectivity solutions, including AMD’s leading 112G technologies.

With over 15 years of experience in high-performance hardware design, Bassam brings deep expertise in complex digital systems and board-level architectures. His background enables him to bridge advanced engineering innovation with real-world customer challenges. At AMD, he works at the intersection of technology and strategy; helping translate cutting-edge silicon capabilities into compelling, system-level solutions that accelerate time to market and enable customers to confidently deploy high-speed platforms.

Signal Integrity at 112G+ with AMD FPGAs: Designing for Margin at the Edge

At 112G PAM4, signal integrity becomes a system-level challenge and not just a PCB problem. With eye margins measured in millivolts and picoseconds, traditional design approaches no longer guarantee success.

This session explores what it really takes to achieve robust 112G+ links using AMD FPGAs. We’ll examine the impact of PAM4 on channel budgets, equalization strategy, and overall link performance, and discuss how silicon capabilities, package effects, PCB design, and connectors must be co-optimized from day one.

Through practical insights and real-world lessons learned, we’ll highlight common failure modes, measurement pitfalls, and design trade-offs that influence first-pass success. We’ll also touch on how these challenges evolve as the industry moves toward 224G.

Bob Storey is CTO of XJTAG. With a degree in electrical and electronic engineering he has spent most of his career writing software, and loves working at the boundary between software and hardware systems. With experience in ethernet networking and security, and the last 20 years spent working at XJTAG, he is passionate about improving best practice across the electronics industry when it comes to bring-up and test of designs in both prototyping and in manufacture.

Making Electronics Under Pressure

Throughout the whole product development lifecycle there is more pressure than ever to move fast and do it right first time. With new PCB technologies such as High-Density Interconnect, blind vias and embedded components becoming increasingly common we will discuss test methodologies and architectures at both device and board level which can help engineers make the right choice for their needs. There is no golden ticket!

Chad Hamilton is Vice President of Products at Molex’s Aerospace & Defense Solutions division. Chad has been in the industry for 30+ years and has spent his entire career in FPGA, ASIC and related technologies. After several years as an FPGA engineer, Chad moved into the field and spent 4 years as an FAE focused on Altera FPGAs. Chad has now been with Molex for the past 18 years and has held roles as Director of Applications Engineering, VP Product Development and most recently, VP of Products. He is actively engaged with customers to understand their requirements and works with the product development team to bring new products to market that address those needs.

RFSoC at the Edge

Molex uses FPGA and RFSoC devices, tools and IP to help customers solve a variety of challenging application requirements. In this presentation, Molex will provide insight into how customers are using FPGA technology within complex systems at the edge and within the datacenters to meet the needs of emerging compute, network, storage and sensor processing workloads.

Goutham Pocklassery is a Senior Member of Technical Staff in the Vivado Product Planning and Tech Marketing team. With over 10 years of experience, he specializes in FPGA design methodologies, AI‑assisted development flows, and adaptive SoC enablement. With a background spanning hardware design, system‑level integration, and advanced verification techniques, Goutham focuses on making complex programmable‑logic workflows more intuitive, automated, and accessible to engineers of all backgrounds.

Agentic AI Workflows for Modern Adaptive SoC Development

Agentic AI is transforming how FPGA developers design, verify, and bring up systems. This hands-on workshop introduces a natural‑language-driven workflow where attendees guide an AI agent through FPGA development, from interpreting design intent to generating hardware and software artifacts. Using intuitive prompts, workshop participants will observe the agent create and integrate AMD Vivado™ block‑design components, configure subsystems, run build flows, and deploy to the AMD KV260 hardware platform. The session highlights a modern, software-centric approach to FPGA development, demonstrating how Agentic AI accelerates iteration, reduces complexity, and enables a full concept-to-hardware experience accessible to engineers of all backgrounds.

Technical workshop prerequisites: Attendees should be familiar with FPGA design tools and bring an open and inquisitive mind.

Hussein Osman leads global initiatives across Consumer and Client Segments, Vision, and Edge AI Solutions. With more than two decades of experience spanning engineering, product marketing, solution definition, and ecosystem development, he sits at the intersection of technology strategy and real-world customer impact.

Hussein’s career is grounded in a deep technical foundation. His expertise spans systems hardware design, embedded systems, computer vision, human‑machine interfaces, and FPGA emulation—experience that enables him to translate complex engineering capabilities into deployable, commercially viable solutions.

Throughout his career, he has worked hands-on across the full innovation lifecycle: from architecting hardware and building core technology blocks, to shaping product roadmaps, to driving large‑scale customer engagements with OEMs, Tier‑1s, industrial partners, and emerging AI innovators.

Efficient Vision Pipelines on FPGAs: Design Patterns and Performance Tuning

Building high-performance vision pipelines on FPGAs requires balancing compute, memory bandwidth, and latency. This talk presents proven design patterns for implementing object detection, segmentation, and defect inspection using FPGA accelerators. We’ll cover Conv-core optimizations, address generator tuning, and leveraging DSP blocks for ML inference. Special focus will be given to sensAI modular IP architecture, enabling developers to scale from simple classification to complex multi-stage pipelines. Real-world benchmarks on CertusPro-NX will illustrate how to achieve sub-10-ms inference while maintaining ultra-low power consumption.

Using Altera’s FPGA AI Suite Software to Implement AI-powered Systems

By reviewing two AI-based example designs, we show the results for low-latency edge inference using Altera FPGAs and Altera’s FPGA AI Suite software.

Firstly, 4K Camera with AI Pose Estimation and secondly, Google’s Magika AI-powered file content-type detector. Using these design examples (free to download), we will highlight recent software updates and explain how they enhance the workflows of data scientists and FPGA developers. Attendees will leave with a clear understanding of what is available now and how to take advantage of these products.

Jamie Tidman is the CTO of Japeto and the technical lead for Japeto’s AI products. He holds an MSc in Computer Science from University College London. Jamie has over 13 years of experience in software development, including 8 in language AI and natural language processing.

Jamie began his career as a software developer for Ocado and OVO Energy, before founding Japeto in 2014. Since then, he has been the principal architect and CTO for a range of software startups, including PSD2 regulated financial institutions and healthcare.

Jamie’s focus is on developing language AI products which handle sensitive data securely, helping organisations like education, healthcare and the space sector safely use the benefits of AI.

Closing the Verification Gap

One of the largest challenges in FPGA design is ensuring the design meets the requirements placed upon it. There are a number of techniques which developers use, from code and functional coverage to requirement tracing and linking.

This session will examine how we can use trained AI models to help identify if RTL code implements requirements placed on it. This approach can be used to assist verification or aid debugging, another advantage is ensuring AI generated RTL contains the functionality requested.

It will include  real world examples of how AI models can be used to detect not only missing requirement implementation within the RTL, but can also be used to verify issues which might exist within the requirements.

The models and approach presented in this session are being developed in conjunction with the European Space Agency.

Jim Lewis has 30 plus years of design and teaching experience and is well known within the VHDL community. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc.  In his design practice, he has created designs for print servers, networking, fighter jets, video phones, and spacecraft. 

OSVVM: A Better Way to Verify Your VHDL Designs

Developing and deploying a verification methodology is costly and time consuming. Going without one is even more costly due to bugs escaping into production hardware systems.

Open Source VHDL Verification Methodology (OSVVM) provides the VHDL community with verification capabilities that rival any other verification methodology – including SystemVerilog + UVM. Yet OSVVM is easier. As a result, it allows any VHDL engineer to write VHDL testbenches, test cases, and verification components for both simple unit/RTL level tests and complex, randomized full chip or system level tests.

With OSVVM you get transaction-based testing, a verification framework, verification components, self-checking tests, messaging handling, error tracking, requirements tracking, constrained random testing, scoreboards, functional coverage, co-simulation with software, test automation, scripts, and a comprehensive set of test reports. This presentation examines the benefits of using OSVVM on your projects.

Mark Fosberry has over 30 years’ industry experience spanning high volume telecom products and complex AI enabled multifunction RF systems. Mr. Fosberry’s wide background spans FPGAs, Software, and RF design, or ‘RF to bits’. This allows for interesting performance trade spaces. He currently performs for the MITRE Corporation as a subject matter expert for DoW projects.

Mr. Fosberry has leveraged JTAG in a novel way, able to run systems at speed through JTAG control and status. This control interface is transportable to ethernet or PCIe allowing for MATLAB scripts to be agnostic to the interface by implementing alternate class methods.

Mr. Fosberry is an adjunct professor at Umass Lowell currently teaching elective graduate level courses in the topics of RF design and test. Mr. Fosberry is on the IEEE International Phased Array Symposium Steering Committee. He also competes in SCCA Formula Vee occasionally.

From Algorithm to Hardware: Applying Model-Based Design to Real-World Designs

Model-Based Design promises faster development, fewer bugs, and smoother hardware integration, but what does that actually look like in practice?

This panel brings together experts from MathWorks and AMD, along with an industry power user to explore how MATLAB®, Simulink™, and AMD Vitis™ Model Composer, along with code generation tools like HDL Coder™ and AMD Vitis™ HLS are being used today to take algorithms from concept to deployed FPGA and adaptive SoC designs. Moderated by Adam Taylor, we’ll discuss where model-based workflows shine, where they still need careful engineering judgment, and how teams are successfully bridging the gap between simulation and hardware reality.

Expect honest insights, practical lessons learned, and a look at what’s coming next.

Mark is an industry veteran with extensive experience in engineering, applications, and marketing. A native of the UK, Mark gained a degree in Electrical and Electronic Engineering from the University of Leeds. During a ten-year tenure with Hewlett-Packard, he managed Engineering and Manufacturing functions in HP Divisions both in Europe and the US before heading up Product Marketing and Applications Engineering at a series of video related startups. Prior to joining Efinix, Mark was Director of Worldwide Storage Accounts at Marvell, heading up Marketing and Business Development activities.

Low Power FPGAs Drive AI to the Edge with Software Defined Hardware Acceleration

This talk will introduce Efinix FPGAs and the revolutionary architecture that delivers unprecedented efficiency. It will discuss the role of these ultra efficient FPGAs in enabling edge AI with agile, turnkey AI acceleration. Acceleration strategies will be discussed that provide a fast time to market in a future proof platform delivering the power and performance profile for edge AI applications. Application examples will be given that showcase the performance improvements that can be achieved while retaining high levels of system integration in a small physical footprint.

From Proven FPGA Innovation to Adaptive Intelligent Systems

We’ll begin by exploring Xilinx’s humble beginnings in FPGA technology before shifting focus to the latest AMD FPGA and Adaptive SoC portfolio. As innovations in design tools continue to evolve, they empower engineers to unlock the full potential of these advanced silicon solutions. Looking beyond 2025, as AI moves from inference toward systems that can sense, decide, and act in the real world, we’ll explore our newest AI solutions for FPGAs and Adaptive SoCs and their role in enabling Physical AI. Finally, we’ll discuss our vision for the future of FPGAs and how adaptability continues to drive the next era of intelligent, real-world systems.

Matthew Burns develops go-to-market strategies for Samtec’s Silicon-to-Silicon solutions. Over the course of 25+ years, he has been a leader in design, applications engineering, technical sales and marketing in the telecommunications, medical and electronic components industries. He currently serves as Secretary at PICMG. Mr. Burns holds a B.S. in Electrical Engineering from Penn State University.

The SGET Open Harmonized FPGA Module™ (oHFM) is Here! – Now What?!

SGET oHFM is the first industry-standard effort focused on SoMs using FPGAs. SGET oHFM solderable modules offer ease of assembly and small form factors for low- to mid-range FPGAs. SGET oHFM connector-based modules allow for larger form factors, increased logic and high-speed SerDes that define high-end FPGAs.

In this technical presentation, embedded experts representing SGET will detail the new specification and various SoM types and sizes. Additionally, expected SGET oHFM uses cases and technical design challenges will also be explored.

An Introduction to Signal Integrity for the FPGA/SoC Designer

The last topic overburdened FPGA/SoC designers ever want to think about is Signal Integrity (SI). However, despite perfect HDL, designing and simulation, synthesis and implementation, and verification and debugging, the system integration on an entire project can be derailed by bad SI design in the end PCB. In this one hour interactive session, technical experts from Samtec will define and illustrate basic SI parameters as well as providing tried and true “rules of thumb” to help FPGA/SoC designers implement their project. In addition, basic tools that help optimize SI along an entire signal chain will also be presented.

Matthew Fransham is a Lead Solutions Architect at Fidus Systems with over 15 years of experience designing and architecting complex embedded systems. At Fidus, he provides system-level technical leadership for high-performance FPGA- and SoC-based platforms, partnering with customers to define robust, timing-critical, and low-latency system architectures.

His background spans FPGA-based systems, processor-centric designs, clocking and synchronization, and complex hardware–software integration. Matthew is known for applying a practical, systems-driven approach to reducing technical risk and guiding teams toward first-time-right execution on high-complexity programs.

He holds an engineering degree and brings deep hands-on experience across the full embedded system design lifecycle.

Learn about IEEE 1588/PTP timing synchronization and distribution within FPGAs, SoCs, and RFSoCs

In this talk, Fidus dives into a compelling discussion on implementing time synchronization and clock distribution in today’s time-reliant embedded systems. They will discuss IEEE 1588/PTP implementations and how the functionality is commonly enabled either solely within, or jointly between, FPGAs, processors, and/or dedicated timing silicon. They’ll share experience of using the locked, recovered clock to generate synchronized sampling clocks for both onboard and multi-board RF/analog frontends (i.e., ADCs and DACs).

Agentic AI Workflows for Modern Adaptive SoC Development

Agentic AI is transforming how FPGA developers design, verify, and bring up systems. This hands-on workshop introduces a natural‑language-driven workflow where attendees guide an AI agent through FPGA development, from interpreting design intent to generating hardware and software artifacts. Using intuitive prompts, workshop participants will observe the agent create and integrate AMD Vivado™ block‑design components, configure subsystems, run build flows, and deploy to the AMD KV260 hardware platform. The session highlights a modern, software-centric approach to FPGA development, demonstrating how Agentic AI accelerates iteration, reduces complexity, and enables a full concept-to-hardware experience accessible to engineers of all backgrounds.

Technical workshop prerequisites: Attendees should be familiar with FPGA design tools and bring an open and inquisitive mind.

Noam Levine is a Partner Manager at MathWorks, focused on the development and promotion of hardware-targeted, application-based workflows. Prior to joining MathWorks in 2008, Noam spent over 16 years in the semiconductor industry in a variety of marketing and application engineering roles. He holds an M.S.E.E. from Northeastern University and a B.S.E.E. from Boston University.

From Algorithm to Hardware: Applying Model-Based Design to Real-World Designs

Model-Based Design promises faster development, fewer bugs, and smoother hardware integration, but what does that actually look like in practice?

This panel brings together experts from MathWorks and AMD, along with an industry power user to explore how MATLAB®, Simulink™, and AMD Vitis™ Model Composer, along with code generation tools like HDL Coder™ and AMD Vitis™ HLS are being used today to take algorithms from concept to deployed FPGA and adaptive SoC designs. Moderated by Adam Taylor, we’ll discuss where model-based workflows shine, where they still need careful engineering judgment, and how teams are successfully bridging the gap between simulation and hardware reality.

Expect honest insights, practical lessons learned, and a look at what’s coming next.

Scott Turnbull is the Chief Technology Officer and Chief Marketing Officer at Fidus Systems, where he has dedicated over 24 years to driving innovation, guiding strategic initiatives, and fostering cross-functional excellence. As a key member of the Fidus Leadership Team, Scott brings a unique blend of deep technical expertise, creative problem-solving, and collaborative leadership.

In his role as CTO, Scott leads a talented team of Solutions Architects, working closely with clients—from nimble startups to global enterprises—to understand their complex embedded system needs, guide product planning, and support technical delivery. His responsibilities span product specification and design, technical oversight, R&D program design, Partner and supplier engagement, and proposal development. A hands-on technologist, Scott remains actively involved in design and development, ensuring engineering rigor and creativity remain at the forefront of Fidus’ solutions.

In 2025, Scott expanded his leadership scope by taking on the role of CMO, where he now oversees Fidus’ Marketing Department.

Throughout his career, Scott has been instrumental in bridging technical innovation with strategic growth. His passion for engineering excellence, global client engagement, and continuous learning has made Fidus his professional home for over two decades.

Learn about IEEE 1588/PTP timing synchronization and distribution within FPGAs, SoCs, and RFSoCs

In this talk, Fidus dives into a compelling discussion on implementing time synchronization and clock distribution in today’s time-reliant embedded systems. They will discuss IEEE 1588/PTP implementations and how the functionality is commonly enabled either solely within, or jointly between, FPGAs, processors, and/or dedicated timing silicon. They’ll share experience of using the locked, recovered clock to generate synchronized sampling clocks for both onboard and multi-board RF/analog frontends (i.e., ADCs and DACs).

Dr. Shahin Tajik is an Assistant Professor in the electrical and computer engineering department at Worcester Polytechnic Institute (WPI). He also serves as the technical co-lead for the Secure Edge Computing area at the Northeast Microelectronics Coalition (NEMC), which has been chosen as an innovation hub for the CHIPS Act’s Microelectronics Commons program. Dr. Tajik earned his Ph.D. in Electrical Engineering in 2017 from the Technical University of Berlin in Germany. His research focuses on FPGA security, side-channel and fault attacks, and the development of tamper detection mechanisms. He is also the recipient of the NSF CAREER Award.

Securing FPGAs against Advanced Physical Attacks

FPGAs have become indispensable components of modern computing systems, powering applications that range from embedded devices to high-performance computing and AI accelerators. While extensive research has addressed threats at the logical and architectural layers of FPGAs, recent studies reveal that attackers can repurpose tools traditionally used in failure analysis (FA) and electromagnetic compatibility (EMC) to exploit the underlying physical characteristics of the FPGA fabric and launch powerful side-channel attacks. In this talk, we first review some of these emerging physical-layer attacks on FPGAs, such as laser voltage probing and impedance analysis, and discuss why conventional protection and detection mechanisms often fail against them. We then explore new approaches to fortifying FPGA-based systems through physical-layer sensing, deception, and moving-target defense strategies.

Ted Speers is a Technical Fellow at Microchip’s FPGA BU, where he is responsible for defining its roadmap for low power, secure, reliable FPGAs and SoC FPGAs. Ted is a RISC-V leader and evangelist and has served on the Board of Directors of RISC-V International since its inception in 2016. He joined Actel (now part of Microchip) in 1987 and held roles in process engineering and product engineering before assuming his current role in 2003. He is co-inventor on 35 U.S. patents. In his role, Ted has consistently defined first-of-it’s-kind products, the most recent example being PolarFire SoC, the first RISC-V-based SoC FPGA. Prior to joining Actel, he worked at LSI Logic. Ted has a Bachelor of Science in chemical engineering from Cornell.

Bitstreams, Backstories & Breakthroughs: A Security Journey in FPGAs

Security in FPGAs didn’t arrive as a monolith. It evolved across generations as we learned what attackers cared about and what users needed. This talk traces that evolution from our anti-fuse roots, through authenticated configuration and side-channel-resistant provisioning, to today’s layered, defense-grade feature sets that make security a built-in property rather than an add-on.

Along the way we’ll share compact, technical stories that changed our trajectory, like the polite note from an independent lab demonstrating device-key extraction via differential power analysis. That single data point galvanized a shift to DPA-resistant cryptography and third-party evaluation, and it shaped how we think about key storage, tamper response and zeroization.

Attendees will leave with a practical timeline of “what, why, and how” of authenticated bitstreams, DPA-hardened flows, PUF-anchored key custody, tamper sensors with deterministic zeroize and secure provisioning chains and guidance on when each control matters. It’s a candid, engineering-level look at how trustworthy FPGAs are built and how those lessons transfer to your next design.

Tommi holds a Master’s degree in industrial engineering from Tampere University of Technology (1999), and carries CISSP, CISA, and CISM certifications.

Common Framework for FPGA-based Hardware Root of Trust

A hardware root-of-trust (HW-RoT) is an essential component for establishing and maintaining digital trust on a computing platform. Solutions offering a range of HW-RoT services for a host system include TPM (Trusted Platform Modules), DICE (Device Identification Composition Engine), and open source implementations such as OpenTitan and Caliptra. Verification and validation of these may prove challenging, especially when applied in high-security assurance scenarios. In this presentation we establish a base for essential HW-RoT functions and requirements, and propose a foundation and architecture for building an FPGA-based Root-of-Trust for enhanced security, lower power consumption, crypto agility, as well as streamlined testing and validation.

The Enclustra SoM – A Smart Foundation for Embedded Systems

Developing modern embedded systems requires balancing performance, reliability, cost and TTM while under tight resource and lifecycle constraints. System-on-Modules (SoMs) offer a proven approach to addressing these challenges by reducing hardware design complexity while maintaining flexibility and scalability.

This presentation introduces Enclustra System-on-Modules as a smart foundation for embedded products, highlighting how they simplify development without compromising performance or long-term maintainability. We will explore Enclustra’s latest SoM offerings, covering key aspects such as FPGA and SoC integration, power management, memory configuration, and high-speed interfaces. The talk will also address practical considerations, including design reuse, risk reduction, and lifecycle support.

Through real-world design examples, attendees will learn how Enclustra SoMs enable faster development cycles, reduce engineering risk, and provide a reliable path from prototype to production. This session is intended for Embedded System Designers, FPGA engineers, and technical decision-makers seeking an efficient and robust platform for next-generation embedded products.

Udayan Sinha is Senior Manager, Product Marketing at AMD. His focus is on enabling High-Performance DSP applications using AMD Versal™ AI Engine technology

From Algorithm to Hardware: Applying Model-Based Design to Real-World Designs

Model-Based Design promises faster development, fewer bugs, and smoother hardware integration, but what does that actually look like in practice?

This panel brings together experts from MathWorks and AMD, along with an industry power user to explore how MATLAB®, Simulink™, and AMD Vitis™ Model Composer, along with code generation tools like HDL Coder™ and AMD Vitis™ HLS are being used today to take algorithms from concept to deployed FPGA and adaptive SoC designs. Moderated by Adam Taylor, we’ll discuss where model-based workflows shine, where they still need careful engineering judgment, and how teams are successfully bridging the gap between simulation and hardware reality.

Expect honest insights, practical lessons learned, and a look at what’s coming next.