US East 26 agenda
If you missed the talks, or would like a refresher, PDF versions of the slides are available to view and download below.
9.30 – 10.15
Keynote: From Proven FPGA Innovation to Adaptive Intelligent Systems
AMD
Martin Charron, Sr. Director, Technical Marketing, AMD Adaptive and Embedded Computing Group
We’ll begin by exploring Xilinx’s humble beginnings in FPGA technology before shifting focus to the latest AMD FPGA and Adaptive SoC portfolio. As innovations in design tools continue to evolve, they empower engineers to unlock the full potential of these advanced silicon solutions. Looking beyond 2025, as AI moves from inference toward systems that can sense, decide, and act in the real world, we’ll explore our newest AI solutions for FPGAs and Adaptive SoCs and their role in enabling Physical AI. Finally, we’ll discuss our vision for the future of FPGAs and how adaptability continues to drive the next era of intelligent, real-world systems.
10.20 – 10.50
Bitstreams, Backstories & Breakthroughs: A Security Journey in FPGAs
Microchip
Ted Speers, Technical Fellow
Security in FPGAs didn’t arrive as a monolith. It evolved across generations as we learned what attackers cared about and what users needed. This talk traces that evolution from our anti-fuse roots, through authenticated configuration and side-channel-resistant provisioning, to today’s layered, defense-grade feature sets that make security a built-in property rather than an add-on.
Along the way we’ll share compact, technical stories that changed our trajectory, like the polite note from an independent lab demonstrating device-key extraction via differential power analysis. That single data point galvanized a shift to DPA-resistant cryptography and third-party evaluation, and it shaped how we think about key storage, tamper response and zeroization.
Attendees will leave with a practical timeline of “what, why, and how” of authenticated bitstreams, DPA-hardened flows, PUF-anchored key custody, tamper sensors with deterministic zeroize and secure provisioning chains and guidance on when each control matters. It’s a candid, engineering-level look at how trustworthy FPGAs are built and how those lessons transfer to your next design.
Efficient Vision Pipelines on FPGAs: Design Patterns and Performance Tuning
Lattice Semiconductor
Hussein Osman, Marketing Director
Building high-performance vision pipelines on FPGAs requires balancing compute, memory bandwidth, and latency. This talk presents proven design patterns for implementing object detection, segmentation, and defect inspection using FPGA accelerators. We’ll cover Conv core optimizations, address generator tuning, and leveraging DSP blocks for ML inference. Special focus will be given to sensAI modular IP architecture, enabling developers to scale from simple classification to complex multi-stage pipelines. Real-world benchmarks on CertusPro-NX will illustrate how to achieve sub-10-ms inference while maintaining ultra-low power consumption.
10.55 – 11.15
Using Altera’s FPGA AI Suite Software to Implement AI-powered Systems
Altera
James Moawad, Field Applications Engineer
By reviewing two AI-based example designs, we show the results for low-latency edge inference using Altera FPGAs and Altera’s FPGA AI Suite software.
Firstly, 4K Camera with AI Pose Estimation and secondly, Google’s Magika AI-powered file content-type detector. Using these design examples (free to download), we will highlight recent software updates and explain how they enhance the workflows of data scientists and FPGA developers. Attendees will leave with a clear understanding of what is available now and how to take advantage of these products.
I Feel the Need for Speed – Recreating the Historic F14 CADC in a FPGA
Adam Taylor, Founder
As a child of the 80s nothing grabbed my imagination like the F14 in Top Gun. What is little known about the F14 is that it contained arguably the world’s first microprocessor, created by Ray Holt and his team at Garret AiResearch, designed in 1968 and shipped in 1971 two years before the Intel 4004.
Due to its military applications this design was secret until 1998. Recently Ray Holt made his logbooks and design notes available. In this session we will look at how we have recreated this microprocessor, in a modern FPGA. We will explore how we used AI to distil the disparate information contained within the notebooks into requirement specifications and verification plans. With a combined requirement set we are then able to create HDL modules, Test Benches, and a simple verification program for the CADC running on a AMD FPGA. If you like fighter jets, computer history and FPGA this is the session for you.
11.15 – 11.25
Break
11.25- 11.45
The SGET Open Harmonized FPGA Module™ (oHFM) is Here! - Now What?!
Samtec
Matthew Burns, Director, Technical Marketing
SGET oHFM is the first industry-standard effort focused on SoMs using FPGAs. SGET oHFM solderable modules offer ease of assembly and small form factors for low to mid-range FPGAs. SGET oHFM connector-based modules allow for larger form factors, increased logic and high-speed SerDes that define high-end FPGAs.
In this technical presentation, embedded experts representing SGET will detail the new specification and various SoM types and sizes. Expected SGET oHFM uses cases and technical design challenges will also be explored.
Low Power FPGAs Drive AI to the Edge with Software Defined Hardware Acceleration
Efinix
Mark Oliver, VP Marketing
This talk will introduce Efinix FPGAs and the revolutionary architecture that delivers unprecedented efficiency. It will discuss the role of these ultra efficient FPGAs in enabling edge AI with agile, turnkey AI acceleration. Acceleration strategies will be discussed that provide a fast time to market in a future proof platform delivering the power and performance profile for edge AI applications. Application examples will be given that showcase the performance improvements that can be achieved while retaining high levels of system integration in a small physical footprint.
11.50 – 12.10
Common Framework for FPGA-based Hardware Root of Trust
Tommi Lampila, Chief Revenue Officer, Partner
A hardware root-of-trust (HW-RoT) is an essential component for establishing and maintaining digital trust on a computing platform. Solutions offering a range of HW-RoT services for a host system include TPM (Trusted Platform Modules), DICE (Device Identification Composition Engine), and open source implementations such as OpenTitan and Caliptra. Verification and validation of these may prove challenging, especially when applied in high-security assurance scenarios. In this presentation we establish a base for essential HW-RoT functions and requirements, and propose a foundation and architecture for building an FPGA-based Root-of-Trust for enhanced security, lower power consumption, crypto agility, as well as streamlined testing and validation.
Making Electronics Under Pressure
XJTAG
Bob Storey, Chief Technology Officer
Throughout the whole product development lifecycle there is more pressure than ever to move fast and do it right first time. With new PCB technologies such as High-Density Interconnect, blind vias and embedded components becoming increasingly common we will discuss test methodologies and architectures at both device and board level which can help engineers make the right choice for their needs. There is no golden ticket!
12.15 – 12.35
RFSoC at the Edge
Molex
Chad Hamilton, Vice President of Products
Molex uses FPGA and RFSoC devices, tools and IP to help customers solve a variety of challenging application requirements. In this presentation, Molex will provide insight into how customers are using FPGA technology within complex systems at the edge and within the datacenters to meet the needs of emerging compute, network, storage and sensor processing workloads.
Securing FPGAs against Advanced Physical Attacks
Worcester Polytechnic Institute
Shahin Tajik, Assistant Professor
FPGAs have become indispensable components of modern computing systems, powering applications that range from embedded devices to high-performance computing and AI accelerators. While extensive research has addressed threats at the logical and architectural layers of FPGAs, recent studies reveal that attackers can repurpose tools traditionally used in failure analysis (FA) and electromagnetic compatibility (EMC) to exploit the underlying physical characteristics of the FPGA fabric and launch powerful side-channel attacks.
In this talk, we first review some of these emerging physical-layer attacks on FPGAs, such as laser voltage probing and impedance analysis, and discuss why conventional protection and detection mechanisms often fail against them. We then explore new approaches to fortifying FPGA-based systems through physical-layer sensing, deception, and moving-target defense strategies.
12.35 – 13.35
Lunch in the Exhibition Hall
13.35 – 14.35
Panel: From Algorithm to Hardware: Applying Model-Based Design to Real-World Designs
Moderator: Adam Taylor, Adiuvo Engineering/FPGA Horizons
Panelists:
Udayan Sinha, Senior Manager, Product Marketing, AMD;
Noam Levine, Partner Manager, MathWorks;
Mark Fosberry, Senior Engineer, The MITRE Corporation / Adjunct Professor at U Mass Lowell
Model-Based Design promises faster development, fewer bugs, and smoother hardware integration, but what does that actually look like in practice?
This panel brings together experts from MathWorks and AMD, along with an industry power user to explore how MATLAB®, Simulink™, and AMD Vitis™ Model Composer, along with code generation tools like HDL Coder™ and AMD Vitis™ HLS are being used today to take algorithms from concept to deployed FPGA and adaptive SoC designs. Moderated by Adam Taylor, we’ll discuss where model-based workflows shine, where they still need careful engineering judgment, and how teams are successfully bridging the gap between simulation and hardware reality.
Expect honest insights, practical lessons learned, and a look at what’s coming next.
Interactive Session: An Introduction to Signal Integrity for the FPGA/SoC Designer
Samtec
Matthew Burns, Director, Technical Marketing
The last topic overburdened FPGA/SoC designers ever want to think about is Signal Integrity (SI). However, despite perfect HDL, designing and simulation, synthesis and implementation, and verification and debugging, the system integration on an entire project can be derailed by bad SI design in the end PCB. In this one hour interactive session, technical experts from Samtec will define and illustrate basic SI parameters as well as providing tried and true “rules of thumb” to help FPGA/SoC designers implement their project. In addition, basic tools that help optimize SI along an entire signal chain will also be presented.
14.40 – 15.00
The Enclustra SoM - A Smart Foundation for Embedded Systems
Enclustra
Tony Richtarich, Senior Sales Manager
Developing modern embedded systems requires balancing performance, reliability, cost and TTM while under tight resource and lifecycle constraints. System-on-Modules (SoMs) offer a proven approach to addressing these challenges by reducing hardware design complexity while maintaining flexibility and scalability.
This presentation introduces Enclustra System-on-Modules as a smart foundation for embedded products, highlighting how they simplify development without compromising performance or long-term maintainability. We will explore Enclustra’s latest SoM offerings, covering key aspects such as FPGA and SoC integration, power management, memory configuration, and high-speed interfaces. The talk will also address practical considerations, including design reuse, risk reduction, and lifecycle support.
Through real-world design examples, attendees will learn how Enclustra SoMs enable faster development cycles, reduce engineering risk, and provide a reliable path from prototype to production. This session is intended for Embedded System Designers, FPGA engineers, and technical decision-makers seeking an efficient and robust platform for next-generation embedded products.
Prevent Late-Stage FPGA Failures with Advanced RTL Linting and CDC Analysis
Aldec
Alex Gnusin, Product Manager
Modern FPGA and SoC FPGA designs push the limits of complexity, performance, and reliability. Undetected RTL coding issues can silently propagate through synthesis and implementation, leading to costly rework, schedule delays, or unexpected failures during hardware bring-up. Identifying these problems early is critical to achieving predictable and reliable FPGA designs.
Advanced RTL linting provides a powerful static analysis approach tailored specifically for FPGA development. By applying hundreds of FPGA-relevant design rules — including vendor-specific synthesizability checks, Clock Domain Crossing (CDC) verification, and reset network integrity analysis—linting exposes bugs, inefficiencies, and design mismatches long before simulation or lab validation.
In this tech talk, we will demonstrate how advanced linting and CDC analysis directly improve FPGA design robustness and development efficiency. Through practical examples, you’ll see how early RTL analysis helps improve code quality, supports design reuse, reduces iteration cycles, and prevents late-stage surprises during synthesis and place-and-route — ultimately accelerating time-to-market while boosting design confidence.
15.05 – 15.25
OSVVM: A Better Way to Verify Your VHDL Designs
SynthWorks
Jim Lewis, VHDL Trainer & OSVVM Chief Architect
Developing and deploying a verification methodology is costly and time consuming. Going without one is even more costly due to bugs escaping into production hardware systems.
Open Source VHDL Verification Methodology (OSVVM) provides the VHDL community with verification capabilities that rival any other verification methodology – including SystemVerilog + UVM. Yet OSVVM is easier. As a result, it allows any VHDL engineer to write VHDL testbenches, test cases, and verification components for both simple unit/RTL level tests and complex, randomized full chip or system level tests.
With OSVVM you get transaction-based testing, a verification framework, verification components, self-checking tests, messaging handling, error tracking, requirements tracking, constrained random testing, scoreboards, functional coverage, co-simulation with software, test automation, scripts, and a comprehensive set of test reports. This presentation examines the benefits of using OSVVM on your projects.
Learn about IEEE 1588/PTP timing synchronization and distribution within FPGAs, SoCs, and RFSoCs
Fidus
Scott Turnbull, Chief Technology Officer & Chief Marketing Officer
Matthew Fransham, Lead Solutions Architect
In this talk, Fidus dives into a compelling discussion on implementing time synchronization and clock distribution in today’s time-reliant embedded systems. They will discuss IEEE 1588/PTP implementations and how the functionality is commonly enabled either solely within, or jointly between, FPGAs, processors, and/or dedicated timing silicon. They’ll share experience of using the locked, recovered clock to generate synchronized sampling clocks for both onboard and multi-board RF/analog frontends (i.e., ADCs and DACs).
Signal Integrity at 112G+ with AMD FPGAs: Designing for Margin at the Edge
Bassam Mansour, Sr. Manager, Technical Marketing, AMD Adaptive and Embedded Computing Group
At 112G PAM4, signal integrity becomes a system-level challenge and not just a PCB problem. With eye margins measured in millivolts and picoseconds, traditional design approaches no longer guarantee success.
This session explores what it really takes to achieve robust 112G+ links using AMD FPGAs. We’ll examine the impact of PAM4 on channel budgets, equalization strategy, and overall link performance, and discuss how silicon capabilities, package effects, PCB design, and connectors must be co-optimized from day one.
Through practical insights and real-world lessons learned, we’ll highlight common failure modes, measurement pitfalls, and design trade-offs that influence first-pass success. We’ll also touch on how these challenges evolve as the industry moves toward 224G.
Closing the Verification Gap
Jamie Tidman, CTO
One of the largest challenges in FPGA design is ensuring the design meets the requirements placed upon it. There are a number of techniques which developers use, from code and functional coverage to requirement tracing and linking.
This session will examine how we can use trained AI models to help identify if RTL code implements requirements placed on it. This approach can be used to assist verification or aid debugging, another advantage is ensuring AI generated RTL contains the functionality requested.
It will include real world examples of how AI models can be used to detect not only missing requirement implementation within the RTL, but can also be used to verify issues which might exist within the requirements.
The models and approach presented in this session are being developed in conjunction with the European Space Agency.
(includes 2o mins break)
AMD Workshop: Agentic AI Workflows for Modern Adaptive SoC Development
Goutham Pocklassery, Senior Member of Technical Staff, Technical Marketing & Product Planning. AMD Adaptive and Embedded Computing Group
Nabeel Shirazi, Senior Director of Software Development, AMD Adaptive and Embedded Computing Group
Agentic AI is transforming how FPGA developers design, verify, and bring up systems. This hands-on workshop introduces a natural‑language-driven workflow where attendees guide an AI agent through FPGA development, from interpreting design intent to generating hardware and software artifacts. Using intuitive prompts, workshop participants will observe the agent create and integrate AMD Vivado™ block‑design components, configure subsystems, run build flows, and deploy to the AMD KV260 hardware platform. The session highlights a modern, software-centric approach to FPGA development, demonstrating how Agentic AI accelerates iteration, reduces complexity, and enables a full concept-to-hardware experience accessible to engineers of all backgrounds.
Technical workshop prerequisites: Attendees should be familiar with FPGA design tools and bring an open and inquisitive mind.
12.30 – 13.30
Lunch
(includes 2o mins break)
AMD Workshop: Agentic AI Workflows for Modern Adaptive SoC Development continues
Location
DCU Convention Center,
50 Foster Street, Worcester, MA 01608