FPGA Horizons Newsletter 15

FPGA Horizons London 26: 11 days and counting

It is not long now until FPGA Horizons. It is only a 11 days away, and we are busy making the final preparations. I cannot believe it is only a year since the first one and the rate at which it has grown both in the UK and US.

I have spent much of the last few weeks putting together demonstrations for the event, including several built around the Explorer board and the CADC F14 example, along with a few other fun FPGA demos that I hope will show a breadth of what we can do with FPGAs, and what the Adiuvo boards in particular are capable of.

Something I have found myself doing increasingly this month is exploring AI, and local AI in particular. Given the nature of much of the work we do in the FPGA world, where designs often cannot leave the building, being able to run models locally opens up some interesting possibilities. It is still early days, and I am very much learning as I go, but I am keen to see how far local AI can be taken as part of a real development flow.

One of the things I have always enjoyed about working with FPGAs is the breadth of applications we get to work on, from aerospace and automotive to industrial and commercial systems. The tools will keep changing and the level of abstraction will keep rising, but the need for deep technical understanding does not go away. If anything, it becomes more important.

I am also hoping to make some very exciting announcements at Horizons about upcoming boards, so watch this space.

Adam Taylor

FPGA Horizons London 26

2 days, 20 technical talks, 3 workshops, 46 exhibitors

We’re nearly at capacity for London 26, but there are still a few tickets available. So if you haven’t registered yet, there is still time. There are also some last remaining slots on the Efinix and Lattice workshops. If you already have your ticket, you can still apply below.

Apply for a workshop place >

With more than 40 vendors exhibiting, London 26 is the perfect opportunity to get all your questions answered – in one day and one place. We’re expecting attendees from over 21 countries, so it’s also the ideal time to find out what your colleagues around the world are working on.

From the blog…

Adam Taylor explores some of the Tech Talks at London 26.

Are you ready for the CRA?

I’ve seen quite a few people talking about the upcoming EU Cyber Resilience Act (CRA) on FPGA forums. Some are favorable, especially from those in the aerospace, defense and medical sectors…

What real‑world configuration and deployment can teach us about FPGA security

For me, the configuration and deployment stage of any FPGA design is the most interesting…

Keep an eye on the horizon

New publications coming very soon

Look out for the latest FPGA Horizons Lab Notes

Our series of Lab Notes which deliver practical engineering guidance, hands on walkthroughs, and reproducible workflows for real world FPGA design challenges have proved to be extremely popular. If you’d like to explore secure system design or image processing, our two latest Lab Notes will be published very soon.

COMING SOON: Designing secure systems: AES-GCM and encryption modes

A practical guide to modern cryptographic system design, explaining AES-GCM, authentication, replay protection, common attack vectors, and the engineering practices required to build secure FPGA-based systems.

COMING SOON: Image processing concepts for Programmable Logic

An introduction to FPGA image-processing architectures, covering sensors, video pipelines, AXI Stream transport, filtering techniques, and the design methods used to build high-performance vision systems in programmable logic.

We’ll let you know when they are available for download. And in case you missed the ones we’ve launched so far, you can Explore Lab Notes here

FPGA Horizons Journal: Issue 5 out October 6th

If you’re attending London 26, you can expect a copy in your swag bag. And if you can’t make the conference, we’ll be sharing the new Journal as soon it launches. In the meantime, here’s a reminder link to the Journals we’ve published so far: Explore Journals 1-4

Industry news

From Sensor to Insight: Production-Ready Single-Chip Edge AI. Proven.

Deploying a neural network to edge hardware sounds straightforward, until you try it. You train a model in PyTorch, get great accuracy, and then face a wall of unfamiliar questions: How do you reduce precision without compromising accuracy? How do you target a specific adaptive SoC? How do you integrate inference seamlessly into real-time video pipelines with minimal development effort? Each of these steps can demand weeks of engineering effort on its own. AMD Vitis™ AI and the Vitis Video Analytics SDK (VVAS) are designed to close exactly those gaps.

Edge AI Deep Dive: How FPGAs Support Challenging Real-Time Smart Vision Application Workloads

Today’s developers have a number of options for matching the right processor to the edge-inferencing job, whether it’s tracking motion, analyzing vibration or interpreting voice commands. In this edition of Microchip Insider, we take a closer look at the special role Field Programmable Gate Arrays (FPGAs) play in the edge AI universe.

Lattice Expands Secure Control FPGA Leadership with New Lattice Mach-N2 Family

Lattice Semiconductor announced Lattice Mach™-N2 FPGA family, extending its long-running secure control FPGA leadership with new devices purpose-built for system control and security in modern infrastructure. Built on the Lattice Nexus™ 2 small FPGA platform, Mach-N2 combines integrated flash, a hardware Root of Trust, and CNSA 2.0-compliant post-quantum cryptography (PQC) with crypto agility for trusted, always-on system control and security across next-generation systems.

Altera Adds Post-Quantum Security to Agilex 3 and Agilex 5 FPGAs

Altera Corporation has announced post-quantum cryptography (PQC) support for Agilex® 3 and Agilex 5 FPGAs. Agilex 3 and Agilex 5 devices now offer PQC-enabled secure boot, helping authenticate trusted device configurations while protecting long-life systems against future quantum-era threats. Beyond PQC-enabled secure boot, the FPGA’s Secure Device Manager (SDM) provides additional security capabilities including bitstream encryption for IP protection, physical anti-tamper support, key management, physically unclonable function (PUF) keys, embedded cryptographic cores, and platform attestation.

Learning

From Data Sheet to Design: Building with AMD Spartan™ UltraScale+™ FPGAs

In this webinar, Adiuvo Engineering, we will work through a real design of the Embedded Systems Plus Tile, a 59 × 59 mm module that supports every device from the SU10P to the SU60P on a single PCB, runs from one 4.5–18 V input, and drops straight into the carrier used by its Spartan 7 predecessor.

Watch here >

colibri: CERN VHDL Common Library released for Everyone to Use

Now, marking its fourth anniversary, CERN has decided to release colibri to the worldwide FPGA community for use in your projects and for contributions.

Find out more >

Generating Gaussian Noise in FPGA using LFSRs and CLT

In this Hackster project by Muhammad Ehtisham, we are run through an introduction to FPGA-friendly Gaussian noise generation, from statistical analysis to hardware IP generation.

Bridging FPGAs with the New Vitis System Device Tree Flow

Jeff Johnson at FPGA Developer has released source code for MIPI over Chip2Chip. Anyone can now reproduce the setup and receive 1080p video from two Raspberry Pi cameras over a 10Gbps serial link.