Ever since the release of ChatGPT in late 2022, I have been fascinated by the possibilities (as well as the potential pitfalls) of using AI. Now it’s everywhere, and in all different flavors, and whether you write code or content, or generate images, chances are AI may be involved somewhere along the way.
In FPGA design and development, I’m seeing it more and more. Tools like Claude Code and ChatGPT are being used to create test bench wrappers and draft automation scripts, as well as “dealing with the garbage-tier UX of modern EDA tools and scripting workflows”, as someone notably commented on a Reddit FPGA thread. Some people like it, others use it reluctantly, and there are a sizeable number of holdouts who prefer not to use it.
Expectations are shifting though. A year or so ago, most engineers treated AI as an optional helper. Now there’s a growing assumption that tools should be able to analyze designs, highlight what matters, and cut down the friction in verification and integration work.
I use it, for example, to generate a first pass of RTL or a test bench, but that’s only after I write a detailed module description and provide coding rules and reuse guidance. With those guard rails around it, it acts as a junior engineer who works quickly with mixed results. The code is good, average or sometimes not quite right, but that’s fine because I review and correct or improve anything it gives me.
So far, the use of AI tools has been driven largely by engineers like me seeking ways to speed up repetitive and tedious tasks. What’s interesting now is that vendors are joining in, exploring how they can adapt their workflows with similar AI interaction and guidance to speed up and ease FPGA development. They’re looking at helping us within the tools we already use, doing some of the necessary but routine and laborious tasks we generally don’t look forward to.
All of which is why the AMD keynote at the FPGA Horizons Conference in London on 6 October is a timely one.
In System‑Level Design meets AI‑Driven Workflows in Modern FPGA Embedded Systems, AMD CVP Kirk Saban will look at the ways advances in AI-driven tools are reshaping FPGA workflows through co-pilot-style interaction for design and verification. He’ll show how those workflows are being applied to everyday design and verification, not as theory but as part of current practice.
It’s a chance to see how the approach helps teams move from an initial concept toward a finished implementation with fewer delays and clearer paths through the design flow. Not by calling on external tools like Claude Code, but using the IDEs we already work with.
