London 26 agenda
Day 1
Tue 6th October
Day 2
Wed 7th October
Please note, there are no Demos on Wednesday (Day 2).
AMD Workshop
08.30 – 15.30
Hansom Hall, St Pancras Hotel
Agentic AI Workflows for Modern Adaptive SoC Development
Michael Hutchison, Senior Director — Customer Experience Engineering, Software, and Solutions
Agentic AI is transforming how FPGA developers design, verify, and bring up systems. This hands-on workshop introduces a natural‑language-driven workflow where attendees guide an AI agent through FPGA development, from interpreting design intent to generating hardware and software artifacts. Using intuitive prompts, participants work with the agent to specify and assemble AMD Vivado™ block designs, configure subsystems, run build and verification flows, close timing, and deploy to an AMD adaptive SoC platform. The session shows how Agentic AI can accelerate iteration and reduce tool-flow complexity while keeping engineering evidence in view, from concept through hardware.
Technical workshop prerequisites: Attendees should be familiar with FPGA design tools and bring an open and inquisitive mind.
08.30 - 09.00
09.00 - 10.20
10.20 -10.40
10.40 - 12.00
12.00 -12.40
12.40 - 14.00
14.00 -14.20
14.20 - 15.30
15.30
Efinix and Lattice Semiconductor Workshops
09.30 – 16.30
Hyde Park, Pullman London St Pancras
9.30 - 12.30
Efinix Workshop – Efinity Flow with RISC-V: Program and Debug on the Eval Board
Harald Werner, VP Sales EMEA and Managing Director EMEA
This hands-on workshop guides participants through the complete FPGA development flow using the Efinity toolchain, with a focus on integrating and debugging a RISC-V soft processor on an evaluation board. Attendees will begin by setting up a project, adding the necessary design files and IP, and configuring I/O using the Interface Designer. The session also covers applying timing constraints with SDC files, generating a bitstream, and programming the evaluation board.
Building on this foundation, the workshop explores practical debugging techniques using JTAG, JTAG Bridge, and built-in tools such as the Debugger and VIO. Participants will learn how to insert debug logic, define trigger conditions, and monitor or control signals in real time.
The second half of the session introduces the Efinity RISC-V IDE, where attendees will open, build, and run an example project on hardware, as well as explore software debugging on the RISC-V core. By the end of the workshop, participants will have gained a clear understanding of the Efinity workflow and how to effectively develop and debug both FPGA designs and embedded RISC-V applications. Attendees will be able to keep the boards for future engineering.
Prerequisites: Attendees should have a basic understanding of FPGA design flows, and should arrive equipped with a laptop running Windows 11 or Ubuntu 20.04, and a USB-A hub to connect the evaluation board. Laptops should also have Efinity 2026.1 with latest patch and Efinity RISC-V 2026.1 installed.
08.30 - 09.15
9.30 - 12.30
12.30 - 13.30
13.30 - 16.30
Lattice Semiconductor Workshop - Lattice Nexus FPGA Hands-On + Agentic AI Workflow Workshop
Matt Holdsworth Matt Holdsworth, Senior FAE
NEW: Introduction to Lattice Agentic AI Workflow with Radiant
Lattice Semiconductor is proud to host an in-person workshop covering our low-density Nexus range of FPGAs and introducing an agentic AI workflow for Lattice Radiant tool chain. In this session, we will work hands-on with SW tools, IPs and Development Kits to provide you with a game-changing experience for embedded applications in a wide range of market segments.
12.30 - 13.15
13.30 - 16.30
16.30
Location
Pullman London St Pancras
100 - 110 Euston Road, NW1 2AJ
LONDON