London 26 agenda

London 26

Agenda

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Day 1
Tue 6th October

Day 2
Wed 7th October

Please note, there are no Demos on Wednesday (Day 2).

8.45 – 9.15

Arrival / Registration / Breakfast

09.30 – 10.50

AMD Workshop Part 1 - Agentic AI Workflows for Modern Adaptive SoC Development

AMD
Michael Hutchison, Senior Director — Customer Experience Engineering, Software, and Solutions

Agentic AI is transforming how FPGA developers design, verify, and bring up systems. This hands-on workshop introduces a natural‑language-driven workflow where attendees guide an AI agent through FPGA development, from interpreting design intent to generating hardware and software artifacts. Using intuitive prompts, workshop participants will observe the agent create and integrate AMD Vivado™ block‑design components, configure subsystems, run build flows, and deploy to the AMD FPGA/adaptive SoC hardware platform. The session highlights a modern, software-centric approach to FPGA development, demonstrating how Agentic AI accelerates iteration, reduces complexity, and enables a full concept-to-hardware experience accessible to engineers of all backgrounds.

Technical workshop prerequisites: Attendees should be familiar with FPGA design tools and bring an open and inquisitive mind.

Efinix Workshop Part 1 - Efinity Flow with RISC-V: Program and Debug on the Eval Board

Efinix
Harald Werner, VP Sales EMEA and Managing Director EMEA

This hands-on workshop guides participants through the complete FPGA development flow using the Efinity toolchain, with a focus on integrating and debugging a RISC-V soft processor on an evaluation board. Attendees will begin by setting up a project, adding the necessary design files and IP, and configuring I/O using the Interface Designer. The session also covers applying timing constraints with SDC files, generating a bitstream, and programming the evaluation board.

Building on this foundation, the workshop explores practical debugging techniques using JTAG, JTAG Bridge, and built-in tools such as the Debugger and VIO. Participants will learn how to insert debug logic, define trigger conditions, and monitor or control signals in real time.

The second half of the session introduces the Efinity RISC-V IDE, where attendees will open, build, and run an example project on hardware, as well as explore software debugging on the RISC-V core. By the end of the workshop, participants will have gained a clear understanding of the Efinity workflow and how to effectively develop and debug both FPGA designs and embedded RISC-V applications. Attendees will be able to keep the boards for future engineering.

Prerequisites: Attendees should have a basic understanding of FPGA design flows, and should arrive equipped with a laptop running Windows 11 or Ubuntu 20.04, and a USB-A hub to connect the evaluation board. Laptops should also have Efinity 2026.1 with latest patch and Efinity RISC-V 2026.1 installed.

10.50 – 11.10

Break

11.10 – 12.30

AMD Workshop Part 2

Efinix Workshop Part 2

12.30 – 13.30

Lunch

13.30 – 14.50

AMD Workshop Part 3

Lattice Semiconductor Workshop Part 1 - Lattice Nexus FPGA Hands-On Workshop

Lattice Semiconductor
Matt Holdsworth Matt Holdsworth, Senior FAE

Lattice Semiconductor is proud to host an in-person workshop covering our low-density Nexus range of FPGAs. In this session, we will discuss SW tools, IPs and Development Kits that provide you with a game-changing experience for embedded applications in a wide range of market segments.

14.50 – 15.20