Keynote: 40 years of FPGA Innovations
Kirk Saban, CVP – Embedded Products, Software & Solutions
Michael Hutchison, Senior Director – Customer Experience Engineering, Software, and Solutions
We’ll begin by exploring Xilinx’s humble beginnings in FPGA technology before shifting focus to AMD’s latest FPGA and Adaptive SoC portfolio. As innovations in design tools continue to evolve, they empower engineers to unlock the full potential of these advanced silicon solutions. Looking beyond 2025, with AI at the forefront of technological innovation, we’ll explore our newest, cutting-edge AI solutions designed for FPGAs and Adaptive SoCs, demonstrating how they are ready to start shaping the future. Finally, we’ll discuss our vision for the future of FPGAs.
FPGA Usage in Trading Systems
Qube Research & Technologies
Bras Patta, Quantitative Technology Director
This talk provides an overview of FPGA usage in trading systems, highlighting their critical role in achieving low latency and deterministic performance. We will explore two representative application examples that illustrate how FPGAs are leveraged to accelerate key components in trading workflows. For each example, we will discuss the underlying architectural choices and examine the technical trade-offs involved, such as latency versus resource utilization, and flexibility versus determinism.
The presentation will also delve into the unique challenges of developing FPGA solutions in the fast-paced and highly regulated financial environment, including development time constraints, and the need for rigorous validation.
Robot-on-Chip: How an Altera SoC FPGA and Associated Toolchain Can Be Used for Highly Integrated Robotics Designs
Adam Titley, Director of Robotics & Network Technologies
Scott Ware, Sr SW Engineer: Robotics & Network Technologies
This session explores the benefits of a modular hardware and software design approach for robotic applications using SoC FPGA devices. By leveraging the flexibility of FPGAs and integrated processing systems, components such as motor controllers, sensor interfaces, and communication protocols can be developed as reusable modules. This modularity enhances scalability, simplifies debugging, and accelerates development cycles. The approach supports rapid prototyping and adaptation to various robotic platforms, from mobile robots to manipulators. Through case studies and demonstrations, we show how this design paradigm promotes efficient reuse, system integration, and long-term maintainability in complex robotics projects across research and industry.
The Golden Age of Computer Architecture: FPGA Edition
Ted Speers, Technical Fellow
In 2018, Hennessy and Patterson declared the dawn of a “New Golden Age of Computer Architecture,” driven by domain-specific architectures, open instruction sets, and closer collaboration between hardware and software. In a series of talks since 2019, Ted has tracked the industry’s progress along that path; highlighting the rise of RISC-V, the growing importance of software/hardware co-design, and the emergence of tools like MLIR and CIRCT, that are reshaping how we build compilers for diverse and specialized compute targets.
In this talk, he’ll revisit those themes with a focus on FPGAs as essential platforms in this evolving architecture landscape. He’ll explore how the vision of agile, domain-specific computing is increasingly reflected in the tools we build, the languages we use, and the systems we imagine. He’ll outline where he believes things are headed: towards a future where compilers bridge the gap from high-level intent to heterogeneous hardware, and where open ecosystems enable faster iteration across the stack. Attendees will walk away with a clear map of where the field is moving, how recent advances fit into the broader architecture renaissance, and how FPGAs are uniquely positioned to thrive in this new era.
Why use ‘COTS’ Modules for your Next System?
Sundance
Flemming Christensen, Managing Director
Sundance designed and manufactured our first ‘COTS’ (Commercial-of-the-Shelf) FPGA module in 1993, based on a newly adopted form factor called “TIM” – and Flemming’s talk will take a journey through history with highlights and benefits of adopted SoMs (System-on-Modules) for a secure and continued supply of FPGA modules.
Solving Your Power Puzzle: Lattice FPGAs’ Path to Uncompromised Low Power
Lattice Semiconductor
Matt Holdsworth, Senior FAE
Tired of compromising performance for power efficiency? This session reveals the engineering breakthroughs behind Lattice FPGAs’ industry-leading low power consumption. We’ll explore our unique approach, showcasing how innovations across silicon process, architecture, and design methodologies culminate in FPGAs that significantly reduce system power. Understand the technical advantages that empower you to design smaller, cooler, and more energy-efficient solutions, all while maintaining the high performance your applications demand.
Powering your FPGA
Ross Barratt, Principal Power Engineer
FPGAs present unique challenges due to their high-performance demands and complex power requirements. As FPGAs continue to drive innovation in applications such as AI, data centers, and high-speed communications, selecting the right power architecture becomes critical. This talk explores the general power needs of modern FPGAs and compares discrete, modular, and PMIC-based power solutions.
Attendees will gain insights into how ADI’s advanced power management ICs and reference designs ensure efficient, scalable, and reliable FPGA performance. The session will demonstrate how ADI’s suite of software tools— including LTspice for simulation, LTpowerPlanner for system-level planning, and LTPowerPlay for configuration and monitoring — streamlines the design process from concept to implementation.
Seeding Trust: Hardware-Based Random Number Generation for Cryptographic Security
Xiphera
Valtteri Allekotte, Field Application Engineer
The quality and security of random number generation are foundational to modern cryptographic applications. In this presentation, Xiphera FAE Valtteri Alekotte explores the design, implementation, and deployment of True Random Number Generators (TRNGs) and Pseudorandom Number Generators (PRNGs) on FPGAs.
The presentation covers hardware-based entropy sources, post-processing techniques, and statistical validation methods to ensure cryptographic robustness. It also demonstrates how a hybrid architecture – the combination of a TRNG including an internal entropy source with a high-throughput PRNG – can be efficiently integrated into FPGA logic to deliver scalable and cryptographically secure randomness. Real-world performance benchmarks, design trade-offs, and security implications are discussed, offering insights into deploying FPGA-based random number generation in real-world systems and applications.
Getting Started with OSVVM, VHDL’s #1 Verification Methodology
Jim Lewis, VHDL Trainer & OSVVM Chief Architect
Developing and deploying a verification methodology is costly and time consuming. Going without one is even more costly due to bugs escaping into production hardware systems.
Open Source VHDL Verification Methodology (OSVVM) provides the VHDL community with verification capabilities that rival any other verification methodology – including SystemVerilog + UVM. Yet OSVVM is easier. As a result, it allows any VHDL engineer to write VHDL testbenches, test cases, and verification components for both simple unit/RTL level tests and complex, randomized full chip or system level tests.
With OSVVM you get transaction-based testing, a verification framework, verification components, self-checking tests, messaging handling, error tracking, requirements tracking, constrained random testing, scoreboards, functional coverage, co-simulation with software, test automation, scripts, and a comprehensive set of test reports. This presentation examines the benefits of using OSVVM on your projects.
You Can’t Fix What You Don’t See – A Plea for Visibility in FPGA
Exostiv Labs
Frederic Leens, CEO
As FPGAs become more complex, the design process has evolved and expanded in scope. Interestingly, tools – and sometimes engineers – have become highly specialised for specific tasks, except for ‘debugging’, which remains a somewhat vague concept that occurs throughout the entire design cycle.
In this talk, we will examine the limitations of traditional methodologies and demonstrate why significantly improving visibility is crucial for effective FPGA design and debugging. We will be reviewing multiple real-world FPGA debug cases, highlighting the role of debugging, validation and testing. This topic has become crucial for many and is key to overcoming the limitations of relying solely on simulation techniques.
The Design Process – FPGA Design Insight from a PCB Perspective
Tomas Chester, Founder and Hardware Design Engineer
Creating robust and efficient PCB designs demands not only technical skill but also a strategic approach from the Hardware Design Engineer’s perspective. This presentation will offer a concise exploration of key considerations in designing the Adiuvo Tile series of custom FPGA System on Module printed circuit boards, focusing specifically on the hardware design lifecycle.
We’ll begin by examining schematic creation, highlighting essential tools and implementation strategies for continuous improvement. A significant focus will be placed on initial PCB Layout and the critical practice of design reuse. We’ll showcase techniques for creating reusable blocks and discuss their profound significance, especially when developing multiple hardware designs from an initial template and integrating with software/firmware projects.
Finally, we’ll address the often-underestimated importance of grounding, using examples from FPGA power distribution and pinouts to illustrate its application in custom connector pinout design. We’ll also briefly touch on BGA routing breakout and provide insights into the “bring-up” phase of a new design. Throughout the presentation, we’ll draw on real-world examples and lessons learned, providing actionable takeaways for PCB designers to avoid common mistakes and streamline their hardware development process.
AMD Adaptive SoC and FPGA Accelerated Application Development in Vitis Model Composer
Avnet Silica
Dr. Baha Hashimi, Embedded Systems Specialist
Developing FPGA applications often reveals a skills gap between algorithm developers working in high-level programming environments and implementation engineers applying algorithms on hardware in low-level programming. AMD’s Vitis Model Composer, a model-based design tool, addresses this challenge by introducing a Digital Signal Processing (DSP) algorithm and data processing pipeline within the MATLAB and Simulink environment, which accelerates FPGA and Adaptive SoC production using automatic code generation.
We will share practical insights on how the Vitis Model Composer development flow enables rapid design exploration of performance-optimized HDL, HLS, and DSP blocks to accelerate the design and development of real-world signal processing applications. We will explore bit-accurate, cycle-accurate simulations, and automated test bench generation, which enable rapid design iterations and efficient hardware validation. Attendees will see detailed block diagrams, code examples, and performance data that demonstrate effective partitioning between programmable logic and Adaptive SoC processing engines.
The talk will highlight key lessons in overcoming verification bottlenecks, integrating custom IP, and leveraging Vitis Model Composer automation to reduce manual, error-prone tasks, resulting in faster time-to-hardware, higher productivity, and improved collaboration between algorithm and hardware teams.
Attendees will gain practical knowledge on how to streamline their FPGA and Adaptive SoC development workflows, while focusing their efforts on value-added algorithm innovation to confidently deliver their applications within tight project schedules.
Introduction to UVVM - with a Taste of the Advanced Features
Espen Tallaksen, Managing Director
Universal VHDL Verification Methodology (UVVM) is currently being used by 27% of all FPGA designers world-wide – and increasing. This is due to the improvements UVVM offers in both FPGA quality and development time. The open source Library and Methodology has the most extensive VHDL verification support available and lets you verify complex designs under test (DUTs) with an enhanced testbench architecture and overview that improves readability and maintainability, and simplifies debugging. And if you have a really simple DUT, then you just use the basic parts of UVVM.
UVVM has been significantly updated through several ESA (European Space Agency) UVVM extension projects over the last few years, and we are currently working on even more new features in tight cooperation with ESA.
Importantly, from day one, UVVM provides a testbench kick start with open source Bus Functional Models (BFMs) and verification components for UART, SPI, AXI, AXI-lite, AXI stream, Avalon MM + Stream, I2c, GPIO, SBI, GMII, RGMII, Ethernet, Wishbone, Clock generator, and Error injector.
This presentation will give you a brief introduction to the basics of UVVM – but also show the most important features and explain how they will help you make a better testbench so that you can develop and test faster and more efficiently.
AIE-ML Implementation of a Low-latency LSTM for Sensor Anomaly Detection
Alpha Data
Andrew McCormick, Technical Director
LSTM neural network models are recurrent machine learning models which can be used to capture the normal state of a system, and predict its future behaviour. This can be especially useful when deployed in applications where the detection of anomalous behaviour is required. Conventional pattern recognition machine learning solutions are difficult to apply here as it can be difficult to acquire enough training data of real anomalies for a model to be trained. However, the recurrent network only relies on training data from normal behaviour, and anomalies are detected when the model can no longer predict the underlying behaviour.
In this presentation we will present the development of a deployable solution suitable for detecting anomalies in spacecraft sensor data. Anomalies which may have to be acted upon quickly, and therefore requiring a low latency, sample by sample processing approach. The design targets the Versal Edge VE2302 device which has 34 AIE-ML engines which are well suited for implementing machine learning layers.
The presentation will cover the low level implementation of template kernels in C++ to support the basic machine learning layers required to implement the anomaly detection. Spacecraft typically have many sensors, and the more complex aspects of how to support a high number of models running concurrently on real time data using both parallelization and time-domain multiplexing of the processing will also be described.
Results presented use models trained on real NASA data obtained from 2 Spacecraft, and comparison of the AIE-ML implementation is made with the ground based GPU model solution, which used offline batch processing.
Accelerating Edge and Datacenter Workloads with FPGA and RFSoC Solutions from BittWare
Craig Petrie, Vice President
As part of the Molex group of companies, BittWare leverages advanced FPGA and RFSoC devices, along with a comprehensive suite of tools and IP, to help customers address a wide range of complex application challenges. This presentation will highlight how customers are deploying FPGA technology within sophisticated systems—both at the edge and in datacenters—to meet the demands of next-generation compute, network, storage, and sensor processing workloads.
A key focus will be the implementation of AMD’s Gen 3 RFSoC, which enables four channels of ADC and DAC interfacing. These are complemented by advanced RF front-end solutions that provide amplification, selectivity, and gain control. The design features high input intercept points, optimized clocking, and precision signal routing—resulting in high dynamic range and low spurious response performance.
To streamline system configuration and control, BittWare offers the RFX-Surfer GUI, a powerful tool for intuitive access to critical parameters. Users can easily configure sample rates, operating frequencies, gain settings, and other key metrics, while also benefiting from comprehensive data reporting and monitoring features.
Join us to learn how BittWare’s hardware and software innovations are enabling high-performance, flexible, and scalable solutions across a broad spectrum of advanced applications.
Targeting the Highest Safety Standards in Single FPGA Solutions
AMD
Tryggve Mathiesen, Sr Field Application Engineer / Principal Member of Technical Staff
This session outlines a practical approach to how new architectural features, IP, tools and methodologies allow the highest safety standards to be addressed with single chip SoC/FPGA solutions in industrial, medical, and automotive applications. Covering design methods including safety, reliability and fault tolerance, it offers a practical overview of functional safety with an FPGA/Processor focus.
Real-Time Hardware Simulation with FPGA
Pablo Trujillo, FPGA Designer
Join this session to explore the potential of FPGAs in accelerating real-time hardware simulation, particularly for power electronic systems. By implementing mathematical models of power electronic circuits directly onto FPGA hardware, we can achieve high simulation speeds and accuracy, crucial for design validation.
Leveraging FPGA for deploying AI in Small Satellites
Réaltra Space Systems Engineering
James Murphy, AI Engineering Lead
The integration of artificial intelligence (AI) into small satellite platforms presents significant opportunities for enhancing autonomy, anomaly detection, and onboard decision-making. However, the limited power, size, and radiation tolerance of spaceborne systems impose stringent constraints on traditional AI deployment.
This work explores the use of Field-Programmable Gate Arrays (FPGAs) as an enabling technology for AI inference in small satellites. Drawing on extensive experience in developing embedded software and machine learning models for flight systems, we present a framework that leverages FPGA architectures to accelerate AI workloads while meeting the operational requirements of small satellite missions. The study focuses on lightweight, resilient models optimized for in-orbit anomaly detection, demonstrating how reconfigurable hardware can balance performance, adaptability, and power efficiency. Additionally, deployment strategies are discussed, including model quantization, hardware-software co-design, and fault tolerance techniques essential for space environments. Experimental validation through hardware-in-the-loop simulations and early flight hardware prototypes highlight the potential of FPGA-based AI to significantly enhance the reliability and autonomy of next-generation small satellite missions.
Efinix mainstream low power, high speed FPGAs for the edge
Efinix Inc
Harald Werner, VP Sales EMEA and Managing Director EMEA
This session provides an overview of the diverse Efinix FPGA families with their different features and where to use them.
Trion FPGAs, for example, enable edge or high-volume applications that need devices optimized for small packages, low power, and volume. Titanium FPGAs feature an enhanced fabric, custom-tailored for the computing demands of mainstream applications. For applications in between, Topaz FPGAs have been refined to support the protocols commonly used for high volume designs.
The usage of the FPGAs in different applications will be shown with examples, along with the development kits for Trion and Titanium. Our software tools will be covered, together with the different IP cores (standard and RISC-V solution), and we’ll show an example of an AI implementation with RISC-V and FPGA logic. For the different acceleration steps we’ll use the RISC-V based custom instruction solution as well as a DMA based solution which needs more FPGA logic but gives you higher acceleration.
Key Criteria for Choosing an RF SoM
Knowledge Resources
Marco Smutek, Key Account Manager
Radio Frequency converter enabled Systems on Modules (RFSoms) are convenient. They take care of all the FPGA’s complex power requirements and memory interfaces, are typically compact and save months, if not quarters in development time. But are they any good? Will you get the same RF performance as you might in a carefully designed chip-down approach. YES — if you source well designed modules. This session highlights the main points to watch out for when choosing your SoM or designing your own solution.
HOG: a system to handle your HDL code on git
University of Birmingham
Dr Francesco Gonnella, Senior Electronic Engineer
Coordinating digital design development among many international collaborators is now a very widespread problem. Guaranteeing firmware synthesis reproducibility and assuring traceability of binary files is instrumental to the success of a project.
With this in mind, we created Hog (HDL on git), a set of stand-alone TCL scripts tackling these issues with no need for any external tool or library. Hog works on Windows and Linux, and provides YAML files to set up, without any additional effort, a working Continuous Integration workflow on GitLab or GitHub Actions.
Hog is also seamlessly integrated into the most common HDL IDEs like AMD Vivado Design Suite/ISE, Intel Quartus Prime, Microchip Libero, and Lattice Diamond. At synthesis time, Hog checks the status of your git repository, assuring absolute control of HDL source files, constraint files, and project properties. It also automatically embeds the git commit SHA and a numeric version into the binary file (automatically renamed and properly stored), guaranteeing traceability.
This session introduces Hog and shows how it allows the IDE GUI to be used normally so that developers can get quickly up to speed, cloning the repository, running the Hog script, and working on their IDE as they would normally do.