Find out more about the journal – and how to contribute.
All journal articles
Why the chip shortage means FPGA designs need a Plan B
How to render cloud FPGAs useless
Rethinking how we build high-performance FPGA/adaptive SoCs
Mike Rather, AMD
Migrating from a legacy FPGA to a modern scalable platform
Rachael Peterson, Concurrent Technologies Plc
Validating your FPGA design: The role of post-layout signal integrity
Dan Binnun, E3 Designers
Introducing Ash, the open-source AI assistant for processing EDA files
Kevin Hubbard, Black Mesa Labs
Hidden verification errors and how UVVM finds them
Marius Elvegård, Inventas
Validating single event resilience of the AMD Versal™ AI Edge Series Gen 2 processing system
Pierre Maillard, Ph.D. & Abhijitt Dhavlle, Ph.D., AMD
Designing for portability with open-source FPGA libraries
Oliver Bründler, Maintainer of Open Logic
Streamlining the FPGA-SoC developer experience
Alexander Wirthmueller, MPSI Technologies
Implementing functional safety in hardware and software
Martin Kellerman, Microchip Technology Germany GmbH
Nikola Velinov, Green Hills Software
OSVVM: A better way to verify your VHDL designs
Jim Lewis, SynthWorks Design Inc
Developing a radiation-tolerant AI platform for space using AMD Versal adaptive SoCs
Pierre Maillard, Ph.D., AMD
FPGA strategies for PCB layouts:
Sparse vs Dense via breakouts
Tomas Chester, Chester Electronic Design
Leveraging FPGAs for deploying AI in small satellites
Dr James Murphy, Setanta Space Systems
A progressive approach to accelerating system-level verificationfor AMD Versal™ adaptive SoC designs
Adam Taylor, Adiuvo Engineering & Training
The Cyber Resilience Act
and what it means for FPGAs
Peter Trott, Microchip
Bridging FPGAs with the Vitis System Device Tree flow
A universal MIPI camera FMC PoC
Jeff Johnson, Opsero
Avoiding costly respins:
The case for pre-layout signal integrity
Dan Binnum, E3 Designers
Simplifying the requirements tracking journey
with the UVVM Requirements Traceability Matrix
Espen Tallaksen, EmLogic
From space to server:
Building resilient FPGAs and SoCs for every radiation environment
Dr. Pierre Maillard, AMD
Meet Hog
Introducing the open-source system for handling your HDL code on Git
Dr Francesco Gonnella, Birmingham University
Why PCB testing needs to shift left to the design stage
Matthew Holder, XJTAG
How logic folding boosts FPGA speeds and reduces footprints
Adam Taylor, Adiuvo Engineering & Training
GEAR UP: Post-quantum cryptography has moved from the classroom to the testbench
Matt Hilbert, FPGA Horizons Journal Editor
FPGA BGAs vs SoMs:
Strategies for a PCB layout
Tomas Chester, Chester Electronic Design Inc
Towards Versal 100G UDP filtering and arbitration for RDMA, Part1
John Mower, University of Washington
Jeff Johnson, Opsero
Why you really should be thinking about power and signal integrity
Dan Binnun, E3 Designers
Accelerating FPGA design using LLMs:
5G peak picker case study
Jie Lei, University of Technology, Sydney
How UVVM can result in faster and better FPGA verification
Espen Tallaksen, EmLogic
The Modular Infrared Molecules and Ices Sensor for ESA’s Comet Interceptor mission
Liam McSherry, University of Oxford
From chaos to clarity:
CDC methodologies for success
Dave Wallace, Blue Pearl Software
Embedded processing in FPGAs
Adam Taylor, Adiuvo Engineering & Training
“But it worked in simulation”
The pitfalls – and the promise – of functional verification
Matt Hilbert, FPGA Horizons Journal Editor
The FPGA Horizons Journal is a pioneering publication that explores and illuminates the evolving landscape of FPGAs.
Think hardware acceleration or high-performance computing, embedded systems or AI-driven FPGA applications, and the FPGA Horizons Journal offers insights into the latest research, industry innovations, and real-world deployments.
With contributions from experts across academia and industry, FPGA Horizons provides a platform for FPGA engineers and designers, managers and key buyers worldwide to stay informed about what’s happening in reconfigurable computing today – and where it’s going in the future.
Have a fascinating technical story to tell?
If you’ve got an FPGA innovation or learnings to share, we’d love to hear about it. Don’t worry if you think you’re not the world’s best writer. Our Editor, Matt Hilbert, has over 20 years’ experience turning complex technical topics into engaging articles. He’ll help hone your story so the sense stays true, whilst making it a great read.
Contact contribute@fpgahorizons.com