There’s a technology landgrab going on. The race for bigger, better, faster AI needs more and more compute power. McKinsey predicts that spending on datacenters to feed AI will reach $6.7 trillion worldwide by 2030 just to keep up. That’s more than the GDP of Germany, the world’s third-largest economy. Oh, and annual global datacenter power demand will also rise from 460 TWh in 2024 to over 1,000 TWh in 2030 according to the International Energy Agency (IEA). That’s enough to power Japan … er, all of Japan.
The thing is, a large slice of the spending is going into the hardware that makes AI possible: advanced-node semiconductors, High Bandwidth Memory (HBM), custom AI accelerators, and advanced packaging. The same kind of hardware used in FPGAs as well as mobile phones, laptops, GPUs, and automotive electronics.
And we’re already seeing the ripples it’s causing. In 2026, datacenters are expected to buy up 70 percent of memory chips produced, up from around 30% in 2022. Companies like Micron, SK Hynix and Samsung have shifted their production capacity away from the consumer-friendly DRAM to the more profitable HBM to meet the demand. As a result, Gartner has predicted PC prices will rise by 17% and smartphone prices by 13%. There’s even a new word for it: the ‘RAMpocalypse’.
It’s happening for FPGAs as well. With foundries prioritizing the manufacture of advanced nodes, high-end FPGA devices have dropped down the queue. Meanwhile, legacy and mainstream FPGAs are marooned on mature wafer nodes where capacity expansion has stalled for years, and foundries are reallocating their remaining capacity to more profitable power-management ICs for AI servers. The result is that across almost all device classes, lead times have increased from around eight weeks to 52 weeks and longer.
And in an ironic plot twist worthy of a bad B-movie, the shortage of FPGAs caused by the increasing demand for those advanced-node semiconductors has limited the supply of FPGAs needed for the equipment to test … semiconductors. How’s that for schadenfreude at work?
Welcome to change … again
None of this is new. We saw a similar situation when the COVID-19 pandemic started in early 2020. Labor shortages, lockdowns and foundry shutdowns broke the supply chain for semiconductors and FPGAs, and costs and lead times increased. Shipping delays and shortages in raw materials caused problems throughout the whole manufacturing process and Bills of Materials (BoMs) became a guessing game. The surge in cloud usage from late 2020 onwards then saw the datacenter and telecommunications sectors buy up available FPGA supplies, leaving other sectors to pick up what little was left.
In many ways, however, it is new. This is not a temporary glitch, it’s a structural shift to a different kind of computing that needs a whole new infrastructure to be built, equipped and maintained over what looks like the long term.
PwC and McKinsey have been analyzing what’s been happening in the semiconductor market and they concur in their opinions. PwC’s 2026 Semiconductor and beyond report and McKinsey’s January 2026 Hiding in plain sight analysis both cite computing and data storage as the fastest growing sector, with AI datacenters and servers a major factor in that growth. PwC expects the revenue share of AI accelerators in datacenter chips to grow rapidly and reach around 50 percent of the total. McKinsey goes further and estimates 62 percent of total growth will stem from leading-edge chips, primarily for AI.
In terms of numbers, PwC forecasts the global semiconductor market will grow from $627 billion in 2024 to $1,030 billion in 2030. McKinsey is more bullish and predicts it will increase from $775 billion to $1,600 billion. Either way, it shows the growth is here, it’s now – and its effect on the supply chain will continue for the coming years.
Both, however, are behind the curve. There is now a brutal supply and demand problem with datacenter hyperscalers fighting over a finite supply of semiconductors. In its Spring 2026 forecast, the World Semiconductor Trade Statistics (WSTS) organization predicted the global semiconductor market would grow beyond $1,500 billion in 2026, and reach approximately $1,900 billion in 2027.
Rather than demonstrating another increase in unit demand, however, a large part of that comes from a surge in prices, with chip makers seeing meteoric rises in revenue. The revenue of Micron and SK Hynix has doubled year-on-year, while Samsung has seen a jump of ~130%.
Quite simply, the market isn’t shipping more semiconductors, it’s charging more for them, showing how tight the supply is – and how strong the demand is.
It’s time for that Plan B
Not normal has suddenly become the new normal. Unlike the pandemic, the current global chip and FPGA shortage hasn’t faded, it’s evolved. AI is taking over advanced node capacity, there are queues around the block for packaging and test lines, and even PCB costs are rising. The result? The FPGA you want may not be the FPGA you can get, and even entire device families may no longer be available.
The old assumption that you could choose one device, optimize around it and order it when you need it may no longer work. The new normal brings uncertainty into the equation. For some, flexibility may move from an option to an ongoing design challenge. That calls for rethinking how to approach FPGA design so that you have a Plan B. An option to move to if your first choice isn’t available.
1. Think about constraint-driven design
Many FPGA engineers have a particular liking for one kind of FPGA, or family of FPGAs. It may be familiarity, it may be that it’s easier to work with, it may simply be We’ve always done it this way. It’s time for a change of tack. With uncertain supply chains, a constraint-driven design approach offers more options. Keep that favored FPGA in mind so you have a goal to aim for but be prepared to move on if you have to.
Constraint-driven design thinks in terms of envelopes rather than specific devices. It defines the timing, resource, I/O, power and thermal, and latency budgets designs must operate within. Any FPGA that meets those envelopes then becomes a viable candidate. To make that possible, interfaces must be kept modular and technology neutral, and the power, clocking and PCB topology designed to accommodate the range of devices in the envelope. When the architecture is built this way, switching devices doesn’t require structural change. Only the device-specific wrappers need to be adapted.
It also opens up fallback options across vendors, families, grades and packages, turning a single device dependency into a set of practical alternatives. In practice, it can transform a 52 week lead time into a 12 week pivot to a different device. No promises on that one, but you get the picture.
2. Design for substitution
The next step is to treat FPGA substitution as a normal part of the engineering process rather than an emergency workaround, by designing the system so that changing devices is routine, predictable and contained. The goal is not universal portability, but controlled substitutability.
That starts with abstracted interfaces. Standardized buses like AXI, Avalon or Wishbone provide stable boundaries that survive device changes. RTL can be written to those budgets rather than to device-specific primitives, for example. Parameterized RTL avoids hard-coded vendor primitives and keeps the logic aligned with the resource envelopes already defined. Clocking and high-speed I/O abstraction layers decouple the design from device architectures, and modular floorplanning keeps functional blocks isolated for easier device changes.
With these practices in place, substitution becomes a matter of adapting the device- specific wrappers rather than restructuring the design. Moving to a different FPGA family is then an engineering task not a months long redesign. Again, no promises, but it will be easier.
3. Pre-qualify multiple FPGA families
The third step is to take single device dependency out of the equation by pre- qualifying more than one FPGA family before a project begins. The idea is simple: maintain a primary device, a secondary device and maybe even a third device, each from different vendors or families, so that a pivot is always possible.
That means keeping the toolchains installed and validated for both the preferred device and fallback devices. Minimal test designs should be built for each family to confirm synthesis, place and route behavior and timing closure. On the hardware side, this readiness can be mirrored by designing the baseboard to accept a modular daughtercard (SOM) or architecting a dual-footprint PCB layout for the alternative devices.
With this groundwork in place, a device shortage becomes an engineering pivot, and a pre-qualified alternative can be introduced soon if the bad news lands.
4. Reduce FPGA resource pressure
The fourth step is to reduce dependence on high-end FPGAs, where shortages are most acute. Heavy DSP, SERDES, and BRAM demands limit fallback options, so lowering resource pressure expands the range of devices that can be substituted.
One approach is to move DSP-heavy workloads to external accelerators or dedicated signal processing ICs. Control- oriented logic can also often be shifted to microcontrollers, freeing LUT and BRAM inside the FPGA.
Where possible, utilizing standard parallel or LVDS interfaces instead of high-speed SERDES lanes keeps the I/O highly portable across vendors. Even partitioning the design across smaller devices can be effective, allowing the system to use families with better availability rather than relying on a single large part.
By lowering the resource footprint, the design becomes compatible with more FPGA families and grades, increasing fallback options and reducing the risk of being tied to a device class where there’s a sudden shortage.
5. Maintain procurement‑driven design reviews
If procurement is part of the design review process, availability becomes a design constraint rather than a late surprise. In a supply environment where device families can disappear into allocation overnight, engineering decisions cannot be made in isolation. Procurement visibility becomes part of the technical workflow.
Each review should include a lead‑time check for the identified devices. Multi‑vendor availability assessments help expose allocation differences, and package‑grade options should be confirmed, since some fallback devices may only be stocked in commercial temperature ranges. Even a simple distributor allocation status check can prevent committing to a device that will be unobtainable.
Treating availability as an engineering parameter keeps the design aligned with supply realities and ensures that the Plan B remains viable throughout the project.
Summary
These aren’t easy times for FPGA engineers. The shortage of FPGAs may mean months of work need to be followed by … er, months of work before the final iteration of an FPGA design gets to first silicon. That’s why availability now needs to be treated as an engineering parameter, so that switching devices becomes a routine, predictable pivot rather than an emergency redesign.
Your fallback strategies may look different from the framework outlined here, but building controlled substitutability into workflows is what will keep projects viable if allocations shift overnight. For practical insights on executing an architectural transition, look to Rachael Peterson from Concurrent Technologies, who has written a timely companion piece for this issue: Migrating from a legacy FPGA to a modern scalable platform
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