Validating your FPGA design: The role of post-layout signal integrity

Post-layout signal integrity is the process of validating that the physical implementation of a PCB supports the performance your system requires and was designed for. Many engineering teams take a reactive approach to signal integrity and this will be the first step they take in the process. Whether or not you perform pre-layout signal integrity, it’s the final opportunity to catch any issues before fabrication, and the significant risks of skipping it become crystal clear.

The primary goal is to verify that the design intent has been successfully implemented and that no issues were introduced during the PCB placement and routing processes. This verification approach typically unfolds in stages, moving from broad automated checks of the entire board to highly detailed, full-channel validation of the most critical links.

Impedance and crosstalk scans

One of my favorite types of post-layout simulation and analysis is to perform automated scans of the entire board (or a subset of traces of interest) for impedance discontinuities and potential crosstalk violations. Electronic Design Automation (EDA) tools like Ansys SIwave make these scans relatively simple to set up, simulate and analyze. What I really love about these scans is that they act as powerful fresh eyes for the PCB layout and signal integrity engineering teams, systematically combing through every trace of interest on the PCB. Their value lies in their speed and comprehensive nature: the scans can quickly identify implementation mistakes or overlooked issues that are difficult to catch in a manual review.

Often, these scans flag problems that seem obvious after the fact. Perhaps a trace was accidentally routed with the wrong width, or a differential pair was routed with the incorrect trace-to-trace spacing, or a signal trace unexpectedly crosses a split or void in a reference plane. These are precisely the kinds of errors that can easily creep into a complex design but can be catastrophic to signal integrity. When you have been working on a PCB layout for an extended period of time, these issues are far too easy to overlook due to design fatigue. Luckily, the EDA tool doesn’t have the same affliction, and can help us see things we might otherwise miss.

Impedance scans analyze the geometry of each trace of interest in relation to its reference plane(s) to calculate its characteristic impedance. The tool then generates a board-wide plot, color-coding any trace that deviates from its target impedance (e.g., 50 Ω single-ended or 100 Ω differential) beyond a specified tolerance. This provides a very easy-to-digest visual report on the impedance control of the entire design.

Crosstalk scans identify potential ‘aggressor’ nets that are likely to couple noise onto adjacent potential ‘victim’ nets. The analysis flags areas where traces run in parallel for too long, or too close together. In Ansys SIwave specifically, generic driver models are used to facilitate a quick analysis and provide prompt feedback, without requiring overly detailed and specific model assignments to potentially thousands of nets on a PCB.

It is important to note that this methodology is not a suitable replacement for the rigorous crosstalk analysis required in high-performance RF systems, which typically demand a full 3D EM solver that can account for all physical geometry including shielding, connectors, and the board enclosure to accurately predict electromagnetic coupling. These automated scans are a powerful tool for general analysis of PCB layout, not a one-size-fits-all solution for crosstalk analysis.

It’s also important to understand the limitations of these scans. Because they do not utilize 3D EM solvers, their accuracy is limited to a certain frequency range. However, they remain an indispensable part of the verification process, capable of catching a wide array of common layout issues. Performing these scans should be standard practice for any modern digital design, as they allow engineers to quickly pinpoint and evaluate potential problems before committing to more time-consuming, full-wave simulations.

S-parameter extraction

After performing board-wide scans, it can often be beneficial to look at a specific representative channel for each major interface type we have routed. The hope here is that the high-speed interconnect has been routed with consistent structures, spacing and methodology, whether through proactive planning or disciplined layout practice. This means we can make a reasonably sound correlation between the performance of a representative channel, perhaps a single lane of a PCIe x16 interface, and the other lanes within that complete interface.

This is accomplished through S-parameter extraction, a process where we convert the physical geometry of routed traces into a proven and highly accurate behavioral model that describes how that geometry affects a signal. The process begins by identifying the nets of interest in the layout and defining ports at their start and end points on our PCB, like the pads of the FPGA, SoC or ASIC footprint and a connector or another partner device. These ports act as the virtual measurement points for our simulations.

Modern EDA tools like Ansys SIwave, Ansys Electronics Desktop, and Siemens HyperLynx are then able to employ powerful hybrid solvers to combine the speed of 2.5D solvers for uniform trace sections (microstrip and stripline routing) with the higher accuracy of full-wave EM solvers for complex 3D geometries like transition vias and BGA breakouts. This approach provides a highly accurate S-parameter model without the prohibitive simulation time of a full 3D solution for an entire PCB.

Once extracted, this ‘as-routed’ S-parameter model can be used in two critical ways.

Standalone interconnect assessment

We can analyze the S-parameter model as a standalone entity to verify its compliance against specific performance targets. This is particularly useful for standardized interfaces that have this type of metric defined in their standards and specifications. The PCI Express specification, for example, defines a return loss target for each segment of the channel. By extracting the S-parameter model of our routed PCB, we can directly compare its return loss against the PCIe specification. This provides a clear pass/fail assessment of that specific segment, allowing us to confirm compliance or identify issues without needing to simulate the entire end-to-end channel.

Full-channel simulation

The other way we can utilize the S-parameters is to use the extracted model to evaluate how the routed interconnect performs as part of the complete system. In many workflows, early simulations when they are performed rely on proxy models and we can now replace them with the S-parameter model of the actual, physically routed interconnect.

By running a full-channel simulation with our ‘as-routed’ data, we can quantify the impact of the physical layout on our design margins. The ideal scenario is one that ends with a full-channel simulation that shows sufficient margins against whatever metrics may be of interest (e.g., COM, insertion loss, return loss, eye-mask measurements or bit-error rate (BER) measurements). While the true pass/fail test is always the physical hardware, a positive result in this final simulation serves as the most comprehensive virtual sign-off possible. It provides the final, data-driven confidence needed to commit the design to fabrication.