Abhijitt Dhavlle, Ph.D. Radiation Effects and RAS Solution Team Architect, AMD
In the first article of this series, we looked at why radiation still matters for modern FPGAs and SoCs, introduced the taxonomy of single-event effects, and outlined the layered mitigation strategies used across silicon, device, and system levels. The second article moved from overview to implementation, showing how radiation affects AI inference pipelines and how fault-aware training on the AMD Versal™ platform reduces datapath errors without additional hardware cost.
This third article turns the focus to the processor subsystem itself. Modern adaptive SoCs do not just run neural networks. They boot operating systems, manage peripherals, coordinate Direct Memory Access (DMA) engines, and handle real-time control loops. All of that processing happens inside a complex multicore processor subsystem that is also exposed to radiation, and characterizing its behavior under particle bombardment requires a different approach than testing a datapath or configuration memory.
No universal benchmark exists for measuring how susceptible a processor is to single-event effects. You can’t simply count bit flips in a register file and call it done. Faults can hide in cache coherency logic, propagate through interrupt controllers, or silently corrupt DMA transfers before anyone notices. To address this, AMD developed a top-down processor validation methodology using its System Validation Tool (SVT), a self-hosted framework that generates constrained-random test traffic across the full processing system. We first introduced SVT on 16 nm AMD UltraScale+™ devices, refined it on the original 7 nm AMD Versal™ architecture, and have now extended it to the Versal AI Edge Series Gen 2 devices. [1, 2]
The results presented here come from accelerated beam testing at two facilities: the Crocker Nuclear Laboratory (CNL) using 64 MeV protons, and the Los Alamos Neutron Science Center (LANSCE) using a broad-spectrum neutron source covering roughly 1 MeV to 600 MeV, to evaluate the single-event error (SEE) response in terrestrial (ground and avionics) environments. The data was measured using more than a million SVT test iterations and a cumulative exposure higher than 1.5 million years of natural sea-level radiation at New York City.
Inside the Versal AI Edge Series Gen 2 processor system
AMD Versal AI Edge Series Gen 2 adaptive SoCs deliver end-to-end acceleration for AI-driven embedded systems, all in a single device built on a foundation of enhanced safety and security. Combining world-class programmable logic with a new high-performance processing system of integrated Arm® CPUs and next-generation AI Engines, these devices enable all three phases of compute in embedded AI applications: preprocessing, AI inference, and postprocessing. These devices are designed to support system implementations targeting ISO 26262 ASIL D, when used within an appropriate system level safety architecture and safety case, without the need for an external microcontroller unit (MCU). [3, 4]
The adaptive SoC integrates programmable logic, AI Engines, DSP Engines, and a multicore processor subsystem on a single 6 nm device. The processing system (PS) alone contains 18 Arm cores: 8 Cortex®-A78AE application processors delivering up to 200k DMIPS, and 10 Cortex-R52 real-time processors providing up to 23k DMIPS. These represent a significant architectural step from the earlier A72 and R5F cores used in first-generation Versal devices.
The low-power domain (LPD) contains the R52 real-time processing unit with tightly coupled memories, low-latency caches, and deterministic access paths. The R52 cores can run in dual independent mode for maximum throughput or in lockstep mode for higher diagnostic coverage. The LPD also hosts the platform management controller (PMC), which handles secure boot, power sequencing, clock control, and domain management.
Communication between these domains, along with the programmable logic and AI Engines, flows over an integrated network on chip (NoC) that provides scalable bandwidth, quality-of-service controls, and global address mapping. This partitioned architecture is important from a radiation perspective because it enables independent power control, safety partitioning, and workload isolation, all of which influence how and where single-event effects manifest.
Testing an entire processor: The System Validation Tool
Testing a processing system for radiation resilience is fundamentally different from testing configuration memory or a neural network datapath. You need to exercise cache fills and evictions, interrupt servicing, DMA activity, peripheral transactions, coherency protocols, and multi-master bus contention, all running concurrently, all checked against known-good results.
SVT is an AMD proprietary, self-hosted validation environment designed for exactly this purpose. It runs natively on the target hardware rather than through external stimuli, thereby validating the platform under realistic execution conditions. The framework can launch hundreds of independent tests per second, creating sustained, high-density system-level traffic across the device. [1, 2]
During radiation testing, SVT initializes with the beam disabled and safety features enabled: processor lockstep modes, redundancy voters, and ECC protection for on-chip and external memories. When initialization completes and execution begins, irradiation is enabled. SVT performs continuous self-checking on every transaction, automatically correcting and logging recoverable faults while continuing execution. Testing proceeds until a non-correctable fault is detected, at which point execution halts and diagnostic data are captured.
Classifying soft error signatures
Not all radiation-induced events are equal, and lumping them together would make the results meaningless for reliability or functional safety analysis. We classify observed events into four categories that directly map to how they affect a deployed system.
Three of these four categories are directly captured through SVT logging. The fourth, safe faults, can be inferred through log analysis. Because SVT generates such high-density traffic across the processor, a dangerous internal fault is unlikely to remain hidden without eventually propagating to an observable system effect.
Experimental setup at the beam
We conducted accelerated beam experiments at two facilities. At Crocker Nuclear Laboratory (CNL), we used a 64 MeV proton beam from the CNL cyclotron, which can deliver high-intensity beams with tunable energies up to approximately 64 MeV. At the Los Alamos Neutron Science Center (LANSCE), we used a broad-spectrum neutron source covering roughly 1 MeV to 600 MeV.
The device under test, a Versal AI Edge Series Gen 2 (XC2VE3858) mounted on a custom AMD evaluation board, was installed in the respective beam lines. After device configuration and processor initialization, we exposed the DUT to radiation until prescribed fluence targets were reached. For statistical confidence, we accumulated total fluences on the order of 1 x 1011 protons/cm2 and 1 x 1011 neutrons/cm2, aggregated from multiple shorter irradiation runs.
Throughout the campaign, more than one thousand radiation-induced upset events were recorded, primarily dominated by cache and RAM SEUs. Over a million SVT test iterations were completed, exercising all the processor’s power domains.
For failure-in-time (FIT) calculations, which translate in the number of errors in a billion hours, we used a high-energy neutron flux of approximately 13 neutrons/cm2/hr at NYC sea level, consistent with commonly used atmospheric models. Using this reference flux and established proton-to-neutron correlation methods, the accumulated test fluence corresponds to an equivalent exposure of approximately 1.5 million years of natural sea-level radiation.1
Single events results summary
The SVT test tool exercised >90% of every accessible block in the processing system. From the beam test measurements, the error coverage per ISO 26262, a measure of how effectively a safety mechanism detects or handles faults in a system, is >99%. Years of AMD beam testing have also confirmed that a 64 MeV mono-energetic proton source serves as a good proxy for terrestrial neutrons above 10 MeV, with published data showing less than 10% error between the two sources on previous technology nodes.[5]
The headline results are worth stating clearly. No single-event latchup was observed across the entire campaign, at a total fluence exceeding 1 x 1012 p/cm2, with the device operating at maximum voltage and 110 degrees C. For cache and RAM single-event functional interrupts (SEFI) events specifically, zero uncorrectable events were recorded under both proton and neutron irradiation. The ECC and safety mechanisms caught and corrected everything that hit those memories.
The overall PS SEFI rate, combining both detectable-uncorrectable and undetected events across all subsystem blocks, measured approximately 2 FIT. To put that in practical terms: with all PS safety mechanisms enabled, you would expect roughly one SEFI every 50,000 years of continuous operation at New York City sea level (baseline per JESD89B std.).1
Distribution of uncorrectable SEFI events in the PS
Looking at the distribution of the SEFI events that were observed, processor trap events (i.e., diverts the CPU from normal execution; if the handoff or handler fails, deterministic behavior or recovery can be lost) were the largest single contributor at 27%, followed by parity errors and UFS traps in the platform management controller at 18% each. NoC network management unit errors, FPX splitter faults (AXI protocol faults that indicate parity), ECC errors in Read/Write AXI channels, DDRMC5 events, and processor hangs (i.e., a fault condition where the processor stops executing instructions and becomes unresponsive) each accounted for approximately 9% of the total. This distribution is useful for system designers because it indicates which recovery mechanisms to prioritize; trap handlers and watchdog timers are the first line of defense for the most common failure modes.
Connecting the pieces
These processing subsystems complement what we presented in the previous two articles. In the first article, we described the three-layer mitigation strategy spanning silicon, device, and system levels and introduced how AMD validates these protections through accelerated beam testing. In the second article, we showed how that strategy extends to AI workloads, where fault-aware training reduced datapath errors by nearly 4X on the original Versal platform. [6]
The Gen 2 results confirm that the architectural improvements carry forward into the processing system as well. The partitioned domain architecture (FPD and LPD), the NoC-based interconnect, and the enhanced safety mechanisms all contribute to containing and managing radiation-induced faults. The fact that cache and RAM SEFIs came back at zero uncorrectable events, while the overall PS SEFI rate sits at approximately 2 FIT, shows that the combination of SEU-enhanced memory cells, ECC protection, lockstep modes, and redundancy voters is working as intended.
For engineers designing systems that need both AI inference and a robust processing system, the practical picture is now fairly complete. The AI datapath is protected by configuration scrubbing, architectural predictability, and fault-aware training. The processing system is protected by domain partitioning, ECC, lockstep, and built-in safety mechanisms.
Suggested best practice for PS testing
Enable every available safety mechanism. The FIT rates reported here assume all PS safety features are active: lockstep, ECC, and redundancy voters. Disabling any of these will increase exposure.
Design recovery paths for common failure modes. Traps and parity errors accounted for the largest share of observed SEFIs. Robust trap handlers and watchdog timers should be part of any high-reliability PS design.
Test the full system, not just components. SVT’s value comes from exercising the entire processing system under realistic workload conditions. Component-level data alone does not capture faults from the interaction of caches, coherency logic, DMA engines, and peripherals operating simultaneously.
Validate your own designs. While vendor-provided FIT data gives a strong baseline, application-specific testing provides the most representative results for your configuration, workload, and environment.
Conclusion
Over the course of these three articles, we have moved from the fundamentals of radiation effects, through AI datapath protection, modes and now into processing system validation. The AMD Versal AI Edge Series Gen 2 results demonstrate that a complex 18-core processing system, operating at advanced 6 nm process nodes, can achieve extremely low SEFI rates when the right combination of silicon-level hardening, on-chip safety mechanisms, and systematic validation methodology are applied.
The testing framework described here, based on the AMD SVT methodology, provides a repeatable approach to characterizing processor soft-error behavior that bridges traditional radiation-effects engineering with functional safety and reliability requirements. As multicore processing systems continue to grow in complexity, this kind of system-level validation becomes increasingly important.
For engineers deploying adaptive SoCs in safety-critical, mission-critical, or long-lifecycle applications, the data presented across this series of articles provides a concrete foundation for design decisions and reliability planning.
This is the third article in a series exploring radiation resilience for FPGAs and adaptive SoCs.
- Read the first article, ‘Building resilient FPGAs and SoCs for every radiation environment’, in issue 2 of The FPGA Horizons Journal.
- Read the second article, ‘Developing a radiation-tolerant AI platform for space using AMD Versal adaptive SoCs’, in issue 3 of The FPGA Horizons Journal.
References
[1] P. Maillard et al., “Heavy-Ion and Proton Evaluation of AMD 7nm Versal Multicore Scalar Processing System (PS),” IEEE, 2023. (https://ieeexplore.ieee.org/document/10265824)
[2] O. Ballan, P. Maillard et al., “Evaluation of ISO 26262 and IEC 61508 metrics for transient faults of a multi-processor SoC through radiation testing,” Microelectronics Reliability, Vol. 107, 2020. (www.sciencedirect.com/science/article/abs/pii/S0026271419303385)
[3] AMD Inc., “Versal Adaptive SoC Technical Reference Manual AM011 (v1.8),” July 2025.
[4] AMD Inc., “Versal AI Edge Series Gen 2 Architecture Overview,” WP565, Automotive Functional Safety White Paper,” (https://docs.amd.com/r/en-US/wp565-automotive-fusa/Versal-AI-Edge-Series-Gen-2-Architecture-Overview)
[5] P. Maillard et al., “Neutron, 64 MeV Proton & Alpha Single-event Characterization of Xilinx 16nm FinFET Zynq UltraScale+ MPSoC,” IEEE 2017 (https://ieeexplore.ieee.org/document/8115449)
[6] P. Maillard et al., “>Proton Evaluation of 7nm Versal AI Engine-Based Radiation-Tolerant Platform for Deep Learning,” IEEE, 2023. (https://ieeexplore.ieee.org/document/10759203)
Footnotes
1. Equivalent years figures are statistical models, not predictions of product lifetime.
