High-performance FPGAs and adaptive SoCs increasingly need to be closely coupled with memory that can keep pace with evolving compute architectures. This is because a lot more is now expected of them. Each new FPGA generation adds more heterogenous compute capability, including upgraded programmable logic and DSP functionality. I/O bandwidth is also growing, with PCIe® Gen6, 100G and 600G Ethernet cores, as well as high-speed serial transceivers, which demand local high-bandwidth memory for storage, buffering, and where necessary, SW application execution.
It’s time to think outside the box
The focus on system-level planning has traditionally guided FPGA design. But we are now seeing a shift toward tighter integration, where device-level considerations sit alongside the system view rather than beneath it. This isn’t done to replace the system perspective, but to free the device from the constraints imposed by DDR-centric architectures. What if the FPGA became the anchor point for this integration, rather than the board? This kind of thinking opens the door to architectures where memory is placed to serve the FPGA, not the other way around. For example, this could bring high bandwidth memory physically closer to the fabric, eliminating the SI/PI, training, and routing constraints that dominate DDR-based designs. Shorter interconnects would also reduce latency and improve determinism for sensitive workloads and real-time systems. And the freed-up routing channels and simplified power domains would give more flexibility in how systems are designed. It could additionally enable compute, fabric, and I/O to scale without being limited. For FPGA engineers, it could also reduce technical risk by removing those design and development stages now necessary. These changes could mitigate DDR-driven board stackups, tight length matching and impedance tuning, and multi-week SI/PI closure cycles. And, importantly, the bring-up issues and problems that can define early hardware validation, including the long debug cycles required to isolate whether faults lie in routing, signal or power integrity, or timing margins could be reduced.
Now let’s think inside the box
This is where a Memory on Package (MoP) approach comes into the picture. If high-bandwidth, low-latency memory is placed directly alongside the FPGA die, rather than outside of it, the existing constraints would be removed. If there’s no external DDR interface to route, there’s no SI/PI envelope to close. With the memory integrated inside the package, it would also effectively remove the memory subsystem as an external attack surface. With no exposed DDR traces, sockets, or byte lanes, the memory path would become extremely difficult to probe, intercept, or tamper with. This would offer a significant advantage for edge‑deployed systems and a solid foundation for meeting security requirements. Instead of shaping the architecture around the memory interface, MoP would allow the architecture to be shaped around the compute again. This would restore the balance between the fabric, I/O, and memory, and enable devices to scale without the constraints imposed by traditional DDR-based designs. Fortunately, this is already happening. Take the new, industry-first AMD Versal™ Premium Gen 2 2VP3622 MoP as an example. Around the same size as a standard FPGA, it integrates 32 GB of LPDDR5X directly inside the package, enabling board sizes to be reduced by ~60%1, and designs to fit into PXI, 3U VPX, and PCIe form factors.
By integrating the external DDR interface, the Versal Premium Gen 2 2VP3622 MoP allows the fabric, processing engines, and I/O to operate at their intended throughput without being gated by board‑level signal integrity constraints. Because the LPDDR5 subsystem is integrated, it removes the high‑speed memory interface, reducing SI/PI uncertainty, simplifying layouts, and cutting weeks to months from bring‑up and validation.
The result is a predictable, factory-calibrated platform that delivers high bandwidth, lower latency, and consistent performance across temperatures and lifecycles. By doing so, it lowers technical risk and shortens development schedules, enabling teams to reach stable hardware and production‑ready designs faster than traditional DDR‑based architectures.
AMD has explored this territory before with the Versal HBM adaptive SoC, which also integrates memory inside the package. However, it does so in a different way by vertically stacking DRAM dies, connecting them with through-silicon-vias (TSVs), and mounting them on a silicon interposer. This delivers massive, multi-terabit per second bandwidth for memory-bound, compute-intensive workloads such as AI acceleration and HPC kernels. That maximum bandwidth does, though, come with trade-offs such as high thermal density, a limited temperature range, and a shorter product availability lifecycle.
This is where the Versal Premium Gen 2 2VP3622 MoP shines, with a fully integrated memory subsystem, a long operating life, industrial temperature robustness, and design simplicity.
What changes when memory moves inside the package
While HBM focuses on maximizing bandwidth, MoP devices address the board-level constraints that limit system performance. Integrating 32 GB of LPDDR5X inside the package removes the footprint and routing penalties of discrete memory devices, shrinking board sizes and freeing layouts that would otherwise be dominated by DDR placement.
With the memory subsystem on-package, the usual SI/PI issues associated with multi-gigabit DDR interfaces fall away, reducing technical uncertainty and making early hardware bring-up far more predictable by lowering risk. The shorter interconnects also improve LPDDR5X performance by removing the losses and conservative margins imposed by board‑level routing and enabling much tighter coupling inside the package.
Eliminating long DDR traces removes a major source of EMI and signal degradation, while the package substrate enables much shorter, tightly controlled interconnects with lower parasitics than traditional PCB routing. The result is a high-performance memory solution with significant technical risk reduced.
And because the memory is no longer dictating placement, power domains, or stackups, MoP devices can be deployed cleanly into VPX and other constrained form factors where it was previously difficult to accommodate several high-speed external DDRs.
Where MoP can make a real difference
The architectural advantages of the Versal Premium Gen 2 2VP3622 MoP translate directly to the kinds of systems that have been pushing hardest against the limits of external DDR.
High-performance networking platforms can take advantage of the connectivity provided by 600G Ethernet, PCIe Gen6, and high-speed transceivers without overwhelming external DRAM. The integrated LPDDR5 also provides the bandwidth and determinism needed for packet buffering, flow control, and real-time analytics.
In aerospace and defense, the on-package LPDDR5 improves security by eliminating exposed memory traces and reducing opportunities for physical probing. Tighter integration also supports established form factors such as VPX, enabling rugged and thermally-constrained designs.
While in test and measurement, the availability of 32 GB of integrated LPDDR5X memory inside the package supports deeper capture buffers and high-rate data processing for oscilloscopes, analyzers, and instrumentation. High-performance PL and DSP blocks also interface cleanly with high-speed analog front ends, enabling more capable and compact equipment.
Similarly, real-time data-processing systems can take advantage of the predictable memory behavior and reduced board complexity, enabling designs that previously required multiple devices or larger form factors. The combination of integrated memory and high-performance I/O opens new possibilities for small-form-factor, power-efficient architectures.
All of these applications can also benefit from the time-to-market advantages of using Memory on Package devices. Starting with a performant, verified, working memory interface reduces the system design effort and can shorten the overall time to get products to market.
Taken together, these capabilities mark a shift in how high-performance FPGA systems can be architected. By removing long-standing DDR constraints, MoP frees FPGA engineers to design what’s needed without restrictions, reduces technical risk, and provides a stable foundation for long lifecycle, industrial temperature deployments. For teams facing rising bandwidth demands and shrinking form factors, it offers a practical and forward-looking path.
Footnote
- Based on AMD internal measurements taken in April 2026, of the board area of a Versal Premium Series Gen 2 MoP 2VP3622 adaptive SoC, compared to the board area of a Versal Premium Series Gen 2 monolithic adaptive SoC with external memory. (VER-111)
