Articles in this issue
Why the chip shortage means FPGA designs need a Plan B
Matt Hilbert, FPGA Horizons Journal Editor
How to render cloud FPGAs useless
Dirk Koch, Heidelberg University
Rethinking how we build high-performance FPGA/adaptive SoCs
Mike Rather, AMD
Migrating from a legacy FPGA to a modern scalable platform
Rachael Peterson, Concurrent Technologies Plc
Validating your FPGA design: The role of post-layout signal integrity
Dan Binnun, E3 Designers
Introducing Ash, the open-source AI assistant for processing EDA files
Kevin Hubbard, Black Mesa Labs
Hidden verification errors and how UVVM finds them
Marius Elvegård, Inventas
Validating single event resilience of the AMD Versal™ AI Edge Series Gen 2 processing system
Pierre Maillard, Ph.D. & Abhijitt Dhavlle, Ph.D., AMD
Designing for portability with open-source FPGA libraries
Oliver Bründler, Maintainer of Open Logic