Building resilient FPGAs and SoCs for every radiation environment
Dr. Pierre Maillard, Radiation Effects and RAS Solution Team Lead, AMD
Radiation-induced single-event effects (SEEs), potentially leading to loss of functionality, high current states, etc., pose major reliability challenges for all electronic systems, from ground-based to space platforms. Modern FPGAs and SoCs are increasingly susceptible due to higher integration densities, smaller feature sizes, and growing on-chip resources. As device complexity and transistor counts rise, so does the likelihood of radiation-induced soft errors, even at ground level, from neutron particles [1]. To ensure reliable operation, robust SEE mitigation at both hardware and system levels is essential to reduce failures and system downtime. However, these protections must be validated through accelerated radiation testing (e.g., heavy-ion or proton beams) to confirm real-world effectiveness. Such tests provide critical insights into system resilience, guiding the design of next-generation radiation-tolerant FPGAs, SoCs, and electronics [1 – 3].
In this article and as an example, we share results from the AMD Versal™ portfolio, including a radiation-tolerant AI-ML platform that has 1 functional interrupt every 60,000 years per AI Engine tile at 40 kft relative to NYC sea level and reduces datapath errors by 3.7X versus the baseline platform [3]. We also highlight a processing system that shows improved single-event resilience by architecture and has 1 event every 6 years in GEO orbit [2].
Why radiation still matters for modern FPGAs and SoCs
From satellites orbiting Earth to high-altitude avionics and autonomous cars at sea level, radiation-induced errors are unavoidable. As process geometries shrink, the susceptibility of SRAM-based FPGAs and adaptive SoCs to single-event effects becomes more pronounced. These events can flip bits, freeze state machines, or disrupt deep learning inference pipelines. Yet, with proper design, detection, and mitigation, radiation effects can be managed rather than feared. For all environments, terrestrial and space designs must consider radiation. Cosmic particles can strike any device at any altitude, and as memory density increases, the statistical likelihood of such events grows.
Real-world examples of radiation-induced events
Over the past two decades, several high-profile incidents have underscored the impact of radiation on electronics. In October 2025, an Airbus A320 flying from Cancún to Newark, NJ suddenly lost altitude due to a radiation-induced computer malfunction. This event led to the grounding of more than 6,000 Airbus aircraft, one of the largest aviation recalls to date, thus causing major travel disruptions [4]. Similarly, in 2021, the Crew Dragon Resilience capsule triggered false emergency alarms aboard the International Space Station, likely caused by a single-event upset (SEU) in an avionics power unit [5]. Even terrestrial systems are not immune: a 2003 voting machine error in Belgium added 4,096 phantom votes, later attributed to a suspected cosmic-ray bit flip [6]. These examples illustrate that radiation-induced upsets can affect systems across environments, from orbit to the ground, and reinforce the need for robust mitigation and validation strategies.
The SEE Taxonomy: Speaking a common language
Single-event effects are disturbances in the normal operation of a circuit or system caused by the interaction of a charged particle with a sensitive node within the device. Depending on their impact and recoverability, SEEs can manifest as soft errors, transient, non-destructive faults, or as hard errors, which may lead to permanent damage.
The most common SEE categories include:
- SEU (Single-Event Upset): A soft error resulting from a bit flip in a memory cell, register, or logic element. SEUs are typically correctable through error-detection and correction (EDAC) mechanisms.
- SET (Single-Event Transient): A temporary voltage glitch induced in combinational logic, which may propagate through sequential elements and manifest as an SEU if latched.
- SEFI (Single-Event Functional Interrupt): A more severe, system-level event that disrupts normal functionality and requires a reset or user intervention to recover.
- SEL (Single-Event Latchup): A high-current condition caused by the activation of parasitic structures within the device, potentially leading to permanent damage if not mitigated.
Radiation-effects engineers, reliability experts, and functional safety architects often use different terminologies to describe similar fault mechanisms. To align these perspectives, AMD has developed a unified classification framework that integrates traditional radiation-effects terminology with Reliability, Availability, and Serviceability (RAS) concepts and Functional Safety (FuSa) metrics. By correlating particle-induced effects with failure modes, mean time to failure (MTTF), and probabilistic safety metrics, this framework supports the development of robust, strategically resilient FPGA and SoC products that address the diverse reliability and safety requirements across markets such as automotive, aerospace, industrial, and data center applications.
Three-layer mitigation: From silicon to system
Our SEE Mitigation Strategy is structured across three complementary layers:
Silicon level: At the silicon level, AMD employs a combination of custom SEU-hardened memory cells, strategic bit interleaving, memory error-correcting codes (ECC), and optimized layout rules to minimize susceptibility to ion strikes. These techniques, together with selective use of triple modular redundancy (TMR), reduce the likelihood of severe events such as SEFIs and SELs.
Device level: Integrated software-based safety mechanisms enhance fault detection and correction capabilities. For example, configuration memory (CRAM) scrubbing and built-in self test (BIST) are used to detect, correct, and isolate soft errors in real time, ensuring system integrity and reducing the risk of error accumulation.
System level: At the system level, system designers or end users can implement additional mitigation. Techniques such as external TMR, voting logic, and configuration scrubbing provide higher-level resilience against cumulative or latent upsets, complementing the underlying silicon and device protections.
I want to emphasize that effective mitigation begins with understanding what must be protected. CRAM typically dominates overall vulnerability, while compiled memories, registers, and control logic require targeted protection strategies. Continuous scrubbing remains essential to prevent the accumulation of silent errors that could otherwise compromise system reliability.
Data-driven validation: Why accelerated beam testing matters
While fault-injection simulations are valuable, they cannot replicate the complex behavior of a charge particle going through silicon, especially multi-cell upset patterns. With uncertainty comes conservativeness and potentially over-engineering for SEE mitigation. This in turn impacts power, performance, and/or area.
Therefore, beam testing using sources such as neutrons, protons, and heavy ions remains critical and the gold standard in industry practice for validating and characterizing the single-event response of FPGA and SoC devices. The AMD test methodology evaluates both the silicon architecture and the effectiveness of mitigation strategies under accelerated radiation exposure, following established industry standards such as JESD89, MIL-STD-883, and ISO 26262.
Experimental results often reveal gaps between predictive models and real-world behavior, particularly within complex blocks such as high-speed SerDes, processor systems, and AI Engines. These empirical insights are crucial for refining mitigation strategies and optimizing the power, performance, and area (PPA) trade-offs in next-generation architectures.
End users are strongly encouraged to validate their own designs (“test as you fly”), since application-specific testing provides more representative results than generic vendor-provided estimates, which may not accurately capture unique architectural configurations, workloads, or system environments.
Examples of beam test results: AMD Versal platforms under terrestrial and space radiation
Processing System (PS)
Since no standardized benchmark currently exists to characterize a processor’s susceptibility to soft errors (e.g., SEU, SET, SEFI), we introduced a new top-down processor validation methodology in the 16 nm UltraScale+™ architecture. This approach leverages the AMD System Validation Tool (SVT), a self-hosted, OS-like validation framework that generates focused random test vectors to thoroughly exercise the full processing system (PS) and associated IPs. SVT provides extensive coverage and was used to demonstrate that the PS fault coverage exceeds 99% [2], including the programmable logic (FPGA) portion of the Versal adaptive SoC.
Accelerated radiation testing using heavy-ion and proton beams demonstrated the robustness of this methodology. Results showed that more than 99.99% of cache and RAM SEU events are correctable under both low Earth orbit (LEO) and geostationary Earth orbit (GEO) radiation environments. Furthermore, for the complete PS, the GEO SEFI rate was measured at approximately 1 event every 6 years, while in LEO at 500 km and 51.6° inclination, the PS SEFI rate was observed at roughly 1 event per year as shown in “Heavy-Ion and Proton Evaluation of AMD 7nm Versal™ Multicore Scalar Processing System (PS)”.[2]
These results confirm that the SVT-based top-down methodology provides an effective and repeatable framework for quantifying and improving soft-error resilience from both reliability and functional safety perspectives.
AI Engine and ML datapaths
Three primary types of radiation-induced error signatures can be observed following a particle strike in a portion of the FPGA or SoC design corresponding to the deep learning model deployment: 1) SEFI, 2) image misclassification errors, and 3) degradation in classification probability/accuracy as shown in “Protons Evaluation of 7nm Versal™ AI Engine (AIE) Based Radiation Tolerant Platform for Deep Learning Applications”.[3] SEFIs are usually manifested as uncorrectable silicon events like system hangs or resets, while the other two types of errors manifest as corruption in the content of the datapath.
To minimize uncorrectable SEFI events at the silicon and datapath level, AMD developed a radiation-tolerant platform for deep learning applications for terrestrial and space systems using a combination of a silicon-level solution such as the CRAM scrubber and a fault-aware training (FAT) methodology. The results showed: 1 SEFI per AI Engine every 60,000 years at 40 kft relative to NYC sea level and a 3.7X decrease in datapath error while eliminating errors with >5% probability degradation. These findings underscore that software-level techniques (like FAT) complement hardware mitigations effectively, achieving radiation tolerance without major performance sacrifices. Details implemented and results from the 64 MeV protons test are available in “Protons Evaluation of 7nm Versal™ AI Engine (AIE) Based Radiation Tolerant Platform for Deep Learning Applications”.[3]
Looking forward: Evolving architectures and methodologies
As modern architectures integrate increasingly complex functions, such as advanced processing systems, AI Engines, and heterogeneous computing fabrics, radiation-effects mitigation strategies must evolve in parallel. Innovation in this domain must progress at the same pace as advancements in power, performance, and efficiency. To accelerate time to market and ensure mission readiness, beam testing should begin early in the R&D cycle, enabling rapid validation of design assumptions and mitigation techniques. Given the limited availability of traditional radiation test facilities, emerging tools such as laser-based fault injection systems (e.g., NRL and third-party platforms) are becoming valuable complements to conventional proton, neutron, and heavy-ion testing. These techniques provide faster feedback during development while maintaining correlation with physical radiation mechanisms.
Consequently, validation and characterization of next-generation FPGAs and SoCs must continually adapt to increasing architectural complexity. Adopting precise error classification schemes, standardized testing methodologies, and consistent reliability metrics is essential both to developing strategic SEE mitigation solutions and to assessing the suitability of FPGA and SoC devices for specific radiation environments.
References
- Weber, Cavin; and Maillard, Pierre. “The Bring-Up: AMD in Space (Part 2).” YouTube, 2024.
- Maillard, Pierre; Chen, Yanran Paula; Arver, Jue; Merugu, Venkatesh; Shui, Ava; and Dhavlle, Abhijitt. “Heavy-Ion and Proton Evaluation of AMD 7nm Versal™ Multicore Scalar Processing System (PS).” IEEE, 2023.
- Maillard, Pierre; Dhavlle, Abhijitt; Chen, Yanran Paula; Fraser, Nicholas; Chen, Yushan; and Vacirca, Nicholas. “Protons Evaluation of 7nm Versal™ AI Engine (AIE) Based Radiation Tolerant Platform for Deep Learning Applications.” IEEE, 2024.
- Baraniuk, Chris. “Bit flips: How cosmic rays grounded a fleet of aircraft.” BBC, 2025.
- McGlaun, Shane. “SpaceX Crew Dragon Capsule Attached to the ISS Sounds False Alarms.” SlashGear, 2021.
- Nappa, Antonio; Hobbs, Christopher; Lanzi, Andrea. “Deja-Vu: A Glimpse on Radioactive Soft-Error Consequences on Classical and Quantum Computations.” arXiv:2105.05103, 2021.
