The case for pre-layout signal integrity
Dan Binnum, Founder, E3 Designers
While sometimes overlooked, signal integrity has an important role to play in the design of modern FPGA and System-on-Chip (SoC) printed circuit board assemblies (PCBAs). Neglecting the principles from the outset can lead to significant design issues, a problem which has become more prominent as data rates rise and the complexity of embedded systems follows in kind.
Too often, engineering teams tackle these challenges in a reactive mode, only looking for problems after the core design work is done. A common workflow is to follow various collections of application notes, rules of thumb, and self-styled best practices that the team may have accumulated over their careers. After finishing the entire design, including schematic capture, PCB layout and the internal review steps required, the team will reach out to an internal or external engineer to perform post-layout signal integrity simulations.
This is where alarm bells should be ringing loudly because the expectation (or rather, the hope) seems to be that the signal integrity exercise will result in a stamp of approval. It’s a matter of checking the box and moving onto fabrication and procurement. There are times, however, when serious issues are discovered that cannot be addressed with simple or straightforward changes. Sometimes there is a fundamental problem with something as basic as a connector choice, pin assignment, PCB material, or stackup design. A problem that can result in significant and costly rework, redesign and lengthy project delays.
A far better approach is a proactive one which allows for the back end of the process to act more as a confirmation step and remain far less disruptive to the workflow. The necessary trade-off, and often a pain-point for management, is the front-loading of signal integrity effort into the early stages of design. It shouldn’t be because the critical work begins long before the first trace is routed on the PCB. This pre-layout phase is where we make foundational decisions and do critical design work that will ultimately determine the success of our designs.
The cornerstones of pre-layout signal integrity
There are four key elements in the pre-layout phase, beginning withcomponent selection. This goes beyond selecting the main FPGA or SoC and includes a holistic view of the entire signal path. From connectors and cables to clock generators and their associated termination components, every aspect of the channel should be considered.
Stackup design and (dielectric) material selection come next, considering the number of layers needed to properly escape from high-density devices. It also means factoring in the frequencies and data rates of interest by choosing suitable dielectric material families.
Simulating a full end-to-end channel with a pre-layout mockup channel analysis is another valuable exercise in understanding the viability of a plan. If you have too much loss in a channel you may need something like a re-timer or re-driver to have a viable channel.This is becoming more common in interfaces such as PCIe Gen 4 and PCIe Gen 5, as frequencies increase and insertion loss rises proportionally.
Finally, we need to consider pre-layout structure optimization. The areas where signals transition from a chip package or connector’s land pattern into the main PCB, the breakout region, are increasingly critical. Before full board layout, we can optimize the specific via structures and trace geometries in these dense regions, minimizing degradation in signal integrity caused by these necessary but disruptive transitions.
Component selection
The primary focus during component selection is on the central FPGA, SoC, or Application-Specific Integrated Circuit (ASIC). Verifying its support for the required protocols and data rates is a fundamental first step. However, a common and dangerous pitfall, especially under tight deadlines, is to assume that a chip supports all features of a given protocol.
This is where a deeper analysis of layout-simplifying features is critical. Two prime examples are polarity inversion (P/N swap) and lane reversal (mapping lane 0…N to lane N…0). When available, these features can dramatically simplify complex routing out of dense packages, potentially saving board layers and reducing manufacturing costs. However, their availability is not guaranteed. A feature may be allowed by a protocol like PCIe, but it must also be explicitly implemented in the silicon of your chosen components. Verifying both levels of support during the component selection phase is essential; an incorrect assumption here can lead to a non-functional interface discovered only after the board has been built.
An even more complex topic is signal equalization, the technique modern transceivers use to compensate for signal degradation. The big takeaway for pre-layout design is the critical importance of simulation models like those using the Input/Output Buffer Information Specification – Algorithmic Modeling Interface (IBIS-AMI). These are the industry standard and the only reliable way to simulate how a chip’s unique equalization scheme will perform in your specific channel. When a vendor does not provide these models, we face a significant challenge. The solution is not to skip the analysis, but to select a suitable proxy model to stand in for the missing component. While this introduces a degree of uncertainty, a simulation based on a reasonable assumption is infinitely better than no simulation at all.Ultimately, every component constituting the high-speed channel must be selected with simulation in mind. Identifying all elements of the signal path, such as the main FPGA, SoC or ASIC connectors, and any off-board cable assemblies or backplane interconnect, and securing their corresponding models early is the foundation of a proactive signal integrity strategy. This approach enables meaningful analysis long before the layout is complete.
Stackup design
Once key components are identified, the design of the physical PCB structure, the stackup, is the next critical pre-layout activity. Every electrical characteristic of a trace, from its impedance to the attenuation it will introduce, is defined by the stackup. Getting this wrong can make a design impossible to salvage, while getting it right lays the groundwork for success.
For example, the insulating material between copper layers is far more than just a physical separator, it’s an active participant in signal propagation. One primary differentiator between material grades is the loss tangent tan(δ).
Standard materials, commonly referred to as ‘FR-4’, are inexpensive but absorb a significant amount of high-frequency signal energy. Use of low-loss materials (e.g., Megtron 6, Tachyon 100G) becomes mandatory when dealing with modern high-speed interfaces. Choosing the material is a fundamental cost vs. performance trade-off that must be modeled and decided upon before any layout begins.
Beyond pure electrical properties like loss, the physical construction of the material is also critical. The woven glass fibers that reinforce the dielectric can create localized inconsistencies. This phenomenon, known as the weave effect, can create a velocity difference between the two traces within a differential pair, introducing timing skew that can corrupt the signal. To combat this, low-loss materials often feature mechanically spread glass weaves to create a more uniform medium. This material-level solution can be further supported by layout techniques such as zigzag routing, where traces are intentionally routed at a slight angle to average out the inconsistencies of the weave.
The other key property to be aware of is the dielectric constant (Dk). This property determines the speed at which signals travel and is a key variable in calculating trace impedance. A consistent dielectric constant across the frequency domain is crucial for consistent performance at high frequencies.
The number and order of layers of copper built around this dielectric material dictates routing capacity, signal isolation, and the quality of the signal return path. High-pin-count FPGAs and SoCs require numerous layers simply to escape all the signals from the Ball Grid Array (BGA) footprint. However, each additional layer adds cost and manufacturing complexity. High-speed signals require an adjacent, uninterrupted reference plane to provide a clean, low-inductance return path. A stackup that sandwiches signal layers between solid reference planes is the gold standard for controlling impedance and minimizing noise and crosstalk.
Vias are necessary to transition signals between layers, but they are also a major source of signal degradation if not planned for. A standard through-hole via can create a long, unused barrel, or stub, which presents a discontinuity at high frequencies, potentially causing signal reflections. The stackup design must account for this, often by specifying that critical high-speed vias be back-drilled (where the stub is mechanically drilled out after fabrication). This adds cost but is often the lowest cost approach to make a high-speed link viable. For extremely dense designs, High-Density Interconnect (HDI) technology using techniques such as via-in-pad, laser-drilled microvias, blind vias, and sequential lamination steps can be necessary. These vias and additional process steps can result in better performance, but they fundamentally change the stackup structure and fabrication process, typically trading cost for increased flexibility and improved performance.
Pre-layout mockup channel analysis
With our key components selected, models gathered and our stackup defined, we can now simulate a full end-to-end high-speed channel. This mockup analysis is, in effect, a dress rehearsal for our design, allowing us to test our foundational choices and ensure they work in concert to deliver a robust and reliable link.
First, we must properly define the channel. For modern protocols like PCI Express, it is the entire signal path from the transmitter’s silicon die to the receiver’s silicon die. This includes the chip packages, the motherboard (or host) traces and vias, one or more connectors, the add-in card traces and vias, and potentially a cable assembly (like a riser cable). Simulating this complete system is the only way to accurately predict real-world performance.
This brings us to a crucial question: how do we simulate a channel that hasn’t been physically laid out or may consist of unknown components? The answer lies in using a combination of vendor-provided models and standardized proxy models. An excellent example of this is the VITA 68.3 standard, which provides a library of S-parameter models for common VPX backplane profiles. A designer can take the model for their proposed PCB trace (based on the stackup design), combine it with the IBIS-AMI model for their chosen FPGA, and connect it to a VITA 68.3 backplane model. This allows us to approximate the system with a reasonable level of accuracy well before it is designed.
The ultimate goal of this exercise is not simply to achieve a pass/fail result, but to quantify our design’s robustness by measuring its margin. One approach for this is utilizing Channel Operating Margin (COM). COM is a sophisticated figure of merit, expressed in decibels (dB), that calculates the signal-to-noise ratio of the link after the effects of the receiver’s equalization are included. It provides a single number that tells us not just if the link works, but how well it works.
The ideal conditions of a simulation – perfect trace geometries, nominal material properties, and quiet power supplies – will never be realized in physical hardware. Manufacturing tolerances and other real-world effects will degrade performance. A healthy margin in pre-layout simulation (for instance, achieving a COM of 6dB where the specification only requires 3dB) provides the necessary buffer to ensure the final, fabricated board meets its performance targets in a real-world environment. Tools such as Siemens HyperLynx support what-if simulations of COM, eye diagrams, eye masks, and bit-error rate (BER).
Pre-layout structure optimization
While mockup channel analysis provides a system-level view of our design, structure optimization is where we zoom in with a microscope. The high-speed signals we implement will not live in ideal traces. They must navigate a series of complex physical transitions from a chip onto the board, through vias to other layers, and through connectors off board. Each of these transitions is an impedance discontinuity that can ultimately cause a link to fail.
The goal of pre-layout structure optimization is to design and validate these critical transitions in isolation before they are used in the PCB layout. Using 3D electromagnetic (EM) field solver tools like Ansys Electronics Desktop or Siemens HyperLynx, we can model these small, complex regions with a high degree of accuracy. The objective isn’t to create a perfect transition; it is to manage the discontinuity, minimize its impact, and characterize its performance.
Fig 3. A 3D EM solved solution for the optimized geometry for the 3D CAD model in Ansys Electronics Desktop
Once a structure is optimized, its model can be saved and handed to the PCB layout team. This creates a library of pre-validated, high-performance building blocks. The layout designer can then confidently place these structures, knowing their performance has already been simulated and approved, drastically reducing design risk.
Over to you
Signal integrity issues extend beyond the PCB layout alone. They affect the workflows of FPGA, SoC, and ASIC engineers and can disrupt entire projects. By shifting signal integrity analysis and optimization into the pre‑layout phase, engineering teams can make informed choices about components, stackup, and critical structures before costly mistakes are baked into the design. This proactive approach transforms simulation from a reactive diagnostic into a predictive design tool, ensuring signal integrity margins are built in rather than hoped for, ultimately reducing risk and minimizing the likelihood of expensive respins.
Want to find out more? Read Dan Binnun’s article, ‘Validating your FPGA design: The role of post-layout signal integrity’, in Issue 4 of the FPGA Horizons Journal.
