Dan Binnun, Founder, E3 Designers
As the capabilities of modern electronics continue to advance, reliable high-speed design has become more and more challenging.
As a result, signal integrity and power integrity are starting to take center stage. Over the past two decades, for example, we’ve witnessed an exponential increase in the data rates of commonly used embedded interfaces. PCIe has evolved from Gen 1.0 speeds of 2.5 GT/s (gigatransfers per second) to Gen 6.0 speeds of 64 GT/s. In addition to increasing Nyquist frequencies, the data encoding schema has grown more complex, evolving from NRZ (Non-Return-to-Zero) to PAM-4 (Pulse Amplitude Modulation with 4 levels). Double Data Rate (DDR) memory has also seen a dramatic increase in speed, with early DDR2 standards running at a few hundred MT/s (megatransfers per second) – and the latest DDR5 standards pushing well beyond 6,000 MT/s.
As is often said in hardware design, everyone wants everything to be faster, smaller and consume less power. This demand for speed extends to all embedded devices, including FPGAs and SoCs which are capable of high-bandwidth data processing and movement. At these speeds, the interconnect carrying our data becomes more difficult to design.
Therefore, more stringent requirements for length matching, impedance control, optimized routing structures and simulation-based performance validation become mandatory for those who want to maximize the chances of success on first revisions of designs.
The networks that provide energy to these devices are also often required to deliver incredible amounts of power with tight regulation and low noise requirements, while being stressed by massive transient load steps. Not only are the power regulators difficult to design and simulate, the PCB copper traces that carry this power are challenging to optimize. Additionally, simulations to assess factors like DC losses from the finite resistance of copper foil and the impedance seen by critical loads (like our FPGAs and SoCs) are also becoming more or less mandatory.
Long gone are the days when we could simply connect components with traces to carry information, use a single ‘VCC’ net, or attach ceramic capacitors with long leads strapped across a DIP socket to decouple our devices. In contrast, for modern devices and designs we must proactively and intentionally optimize signal interconnect and power delivery networks.
The design and simulation of these aspects of PCB design are what many of us in the industry mean when we refer to signal and power integrity – how we connect these components, and how we power them.
In an embedded system or PCB design, components often include your favorite FPGA or SoC. And this does not necessarily mean a high-end SoC like an AMD Zynq UltraScale+, Microchip PolarFire, or Altera Agilex 7. Today, even lower-cost, lower-speed devices support older generations of interfaces, which, while less challenging to design for, are very much non-trivial and should be treated as such.
Signal Integrity
Signal integrity at its most fundamental level is a way to assess the quality of electrical signals and is important in high speed digital systems like those designed around FPGA and SoC devices. Low-Power Double Data Rate (LPDDR) memory, PCI Express, USB 3.x, SATA, multi-Gigabit Ethernet and many more interfaces are extremely common in modern designs. Engineers must consider a wide range of factors when designing these interfaces into a system. These include component selection; PCB material choice and stackup design; and trace width and space considerations with breakout routing subject to different constraints than those in general PCB routing field areas. Via sizes and spacing (for both transition vias and component breakout regions) as well as channel characteristics like insertion and return loss all play a role in ensuring a robust interface.
Fig 1. Eye Diagram Simulation
In many cases, the types of analyses performed depend on the interface being tested. For the sake of discussion, we can consider basic signal integrity analysis, DDR analysis and Serializer/Deserializer (SERDES) analysis, often referred to as high-speed serial input/output (HSSIO). Failure to consider these design aspects can lead to issues such as reduced data rates, increased bit errors, and even the failure to properly train DDR memory or establish viable high-speed serial channels. These problems can result in incredibly expensive re-spins for businesses and engineering teams – and without knowing what to analyze or further investigate, the problems can seem daunting and even unsolvable.
Power integrity
Power integrity refers to the quality of the power delivered to system components, and analysis – or a series of analyses – and can help to determine whether voltage and current requirements are met. The key considerations are mostly related to PCB stackup design for copper weights, dielectric thicknesses for embedded capacitance, and the trace widths necessary to carry currents with an acceptable DC drop. For plane impedance, it is not as simple as providing enough decoupling capacitors of the right type (dielectric) and value (amount). The mounting inductance becomes important, as does the physical construction of the capacitors themselves.
Power integrity has several key factors that should be considered and analyzed during the design phase of a product, including DC drop analysis, target impedance analysis, and simultaneous switching analysis. Without a properly designed power delivery system various issues can occur such as an increased bit-error rate (BER), reduced timing margin, and in some cases even brown-out conditions within devices due to excessive and uncompensated voltage drops during high-load conditions.
Conclusion
Signal and power integrity are more important now than ever before in embedded system design. This trend is unlikely to reverse as the world wants to continue to process more data, more quickly, in more devices. Everything from our cell phones to toaster ovens is featuring some type of wireless or wired connectivity and as these devices become more capable and perform more computing at the edge, we should expect that the FPGAs and SoCs inside them will integrate higher data-rate interfaces into their silicon. Becoming familiar with potential problems and how to get ahead of them will be a major concern for all embedded systems engineers.
In the next installment of this series, we will look in a bit more detail at signal integrity – when we should start considering it (spoiler: as soon as you start a design), what some of the steps might be in signal integrity analysis and simulation, and even a high level process that can be followed to try to ensure success on your high speed designs.
