Strategies for a PCB layout
Tomas Chester, Hardware Designer and Founder, Chester Electronic Design Inc.
All PCB designs bring their own nuance and complexity, and with modern designs using FPGAs, this is even more so due to their flexible nature and configuration ability. Add in the difficulty of signal and power integrity, dielectric materials, other component requirements, and even the overall solvability of a design, and creating a functional PCB layout becomes quite a challenge.
There have been multiple attempts to reduce these intricacies. Reference designs, Custom Off-the-Shelf (COTS) products, and development boards have become increasingly full-featured. This enables their use as a complete replacement or design reference to ease the development of our own solutions. System-on-Modules (SoMs) offer a flexible and efficient design approach, albeit one that brings some of its own problems like cost and feature control. Conversely, FPGA Ball Grid Array (BGA) packages provide high density connections with a small footprint. The approach you use will change how you plan and implement a design so let’s compare and contrast them by focusing on the AMD Xilinx Kria K26 SoM and the AMD Xilinx BGA-676 packaged FPGA.
The AMD Xilinx Kria K26 is a highly capable SoM featuring a Zynq UltraScale+ MPSoC, with DDR4 memory, storage, and power. By having these elements on the module, any carrier board design has its design complexity reduced, speeding up both project timelines and product releases. The Kria module utilizes two high density Samtec ADM6 connectors, each with four rows and 60 columns, totaling 240 pins each. The organization of the pins in four rows that are not equally spaced adds to some breakout complexity.
The BGA-676 package can have a number of different internal interface elements, allowing for a proper comparison to the Kria module. Depending upon the selected FPGA, it has GTH or GTY High Speed Interfaces, HD I/O and HP I/O connectivity, all within a 1.0mm pin spacing. A visual comparison between the Kria module connectors and the BGA-676 can be seen in Figure 1:
Planning the power delivery network
Having outlined the features of each implementation, we can begin by considering the power interface locations. With an FPGA BGA design, it is important to ensure that the power delivery network (PDN) is robust. With a large number of the core power pins located in the center, ensuring appropriate decoupling capacitance and capacitor location becomes critical. Capacitors, typically being of a slightly larger value size to assist with the PCB inductance due to the through vias within the design, are placed on the opposite side of the board from the BGA package.
A good decoupling implementation requires that there either be a very short trace connecting the pads of the decoupling capacitor back into the BGA and/or Power Plane, or that the vias be placed directly in the capacitor pad. This via-in-pad style approach does save additional space and improve performance, however it comes with additional manufacturing requirements and costs. All of this is done to improve the inductive loop area where the power is being used/distributed, while also ensuring that there is enough capacitance for the device. With higher speed designs, the need to create internal PCB planar capacitors will assist with the PDN requirements.
Meanwhile, FPGA I/O banks require their own power on the outer perimeter sections of the BGA package. Highlighting these FPGA I/O banks, they appear almost as a slices or sections in the overall package design. They can have capacitors on the same side as the BGA, as long as there is enough clearance space to allow for inspection and cleaning of the assembled PCB. Alternatively, opposite board side capacitor placement is also valid depending upon the BGA size. Within Figure 2 you can see the highlighted power pins in yellow, with ground highlighted in green.
It is important to note that the decoupling capacitors used with the BGA package are required to be both bulk capacitors as well as smaller ceramic capacitors, to enable rapid responses of large and/or momentary power demand fluctuations.
In comparison, the Kria Module connectors do not require these high frequency response capacitors because there are only four rows of pins and local power supply, device, and FPGA decoupling is provided on the Kria Module. This results in only larger bulk capacitors being required near the connector. This lends to flexibility in capacitor placement, enabling opposite side of the board placement, or same side placement with reasonable proximity. This also enables single-sided design, reducing board assembly costs and complexity. The Kria Module therefore reduces the overall number of capacitors required for placement, resulting in a much simpler, low effort, low time design. For comparison purposes, the image showcases the ground pads also highlighted in green.
Planning the breakout strategy
Now with an understanding of the power pin distribution, we can examine possible breakout strategies. We’ll start with the Kria Module connector because it’s easier than a BGA connection scheme. This is due to the ease of access provided by the spread of interface pads into a rectangular shape as well as the connections being spread over two connectors (only one is shown to allow for higher detail images). However, the connector does have a puzzle element due to the pad matrix having a 0.635mm by 0.96mm grid spacing. This tight pad spacing causes some difficulty in how we break out the routing from the connector.
For our example, we will break out all four rows of pads in the same direction, simulating an outer board edge requirement that determines the routing direction. Showcased in Figure 3, the breakout routing on the left of the connector transitions to vias, while the routing on the right does not. This forces connections on the left outer rows of the high-density connector to be routed back to the right under the connector on other routing layers. Due to the spacing of the pads, the pad matrix does require an intelligent breakout strategy to get between that 0.635mm spacing. While the use of High-Density Interconnect (HDI) or other complex board fabrication techniques can be used and will be examined later, a breakout can be completed using standard manufacturing methods with mechanically drilled through-vias and appropriate copper spacing.
The showcased image shows how slightly offsetting the trace/via breakout with a small angle out of the pads, as well as tightening the via distance to the pad itself, enables standard board fabrication methods. The strategic placement of vias enables the creation of routing channels (shown in blue), enabling those outer connector pads that need to be routed back into the center of the carrier board to traverse the created via field. This slight angular placement within the connector breakout takes special care to ensure via-to-via spacing and via-to-pad spacing to enable general fabrication requirements.
In comparison, trying to break out traces and vias for the BGA has a different strategy. With the density of connections, but also the increased depth due to the 26 x 26 pad grid, routing channels not only need to be created, but managed with this increased concentration. One of the primary ways to accomplish this is to create a quadrant layout. Here, the part is divided in half, both vertically and horizontally, with each of the four resulting quadrants being routed out to their respective outside corner. This is accomplished by placing a small trace section from each pad that enables a via to exist within the grid of the original connection and the other three pads surrounding the via.
This leads to a visual style similar to a dog bone, while again enabling standard PCB fabrication methodology due to the use of standard mechanically drilled through-vias and adequate copper spacing. While alternative breakout methods utilizing HDI techniques do exist, with this BGA-676 having a 1.00 mm pitch, we don’t run into some of the common pitfalls that exist with smaller grid packages. We will not have neck-downs or impedance discontinuities due to copper spacing complexities of 0.8mm or smaller pad pitch packages.
From our previous capacitor decoupling, Figure 2, we saw that the grounds (in green) are evenly distributed over the FPGA. This distribution along with a solid ground plane on layer 2 of our design ensures an excellent return path for the FPGA interfaces. Performing the connection breakout in one of the quadrants creates a via grid that will be utilized in the future. This via grid creates a guide for our routing by creating channels within the PCB, while also allowing better power distribution to the FPGA core thanks to the broad copper section between quadrants (shown in blue).
Planning HDI fabrication techniques
So what about the alternative of using HDI fabrication techniques for the breakout of both the Module connector and the chip-down FPGA package? One of the first HDI options available is via-in-pad which reduces the overall breakout size of both designs by removing the need for any trace sections off the pad. The true advantage with via-in-pad is the ability to place the vias directly into the decoupling capacitors pads either on the other side of the board or into the perimeter capacitors surrounding the BGA or Module connector.
While a minor reduction in the overall breakout and routing space of both components does occur, the use of via-in-pad is actually detrimental. Within the BGA, the reduction removes the wide copper ‘+’ shape that existed from the quadrant layout, which supported power delivery to the center core of the FPGA. Within the Module, the impact is even worse. Due to the close nature of the 0.635mm pad-to-pad grid, the vias being placed within the pads blocks any possible routing channels due to copper clearance requirements. This prevents a breakout of the signals that need to be routed from the left most row under the connector to the right, bypassing the other three rows.
With via-in-pad being a bust then, what about using blind and/or buried vias? For our blind vias we will consider them to be microvias, meaning multiple single layer drills, rather than a single multi-layer drilled blind via. Using this HDI via stack-up design, the breakout can be performed by accessing layers one at a time. Care must be taken to not route on a ground or power distribution layer. However, this opens up options by allowing, in the Module connector case, the breakout to occur without impacting layers further inside the PCB stack-up. With no vias present in these lower internal layers, routing channels do not need to be created as traces will not encounter any via obstructions. This allows us to freely route on layers further away from the connector.
In the case of the BGA package, this same freedom is also allowed. The creation of a different style of breakout can be applied to the BGA package. An example of this microvia structure break can be seen in Figure 4. With its reduced via pad size, multiple vias can be placed inside the four pad grid setup that previously only accommodated a singular through-hole via. This modified breakout shown in the images then increases the number of wide routing channels, instead of the previous two that existed thanks to the central ‘+’ quadrant spaces. Of course, with access to this and other HDI fabrication capabilities, other routing breakout options and routing solutions exist, so experimentation and adaptation to meet your design requirements will be required.
Planning additional routing requirements
Depending upon the utilization of the Module or the chip-down FPGA, we come to the discussion on how to route to the other areas of the design. This becomes highly dependent upon what interfaces we are working with, what speeds we are running at, and how many of the overall connections into and out of the Module/BGA package we need to implement. These will impact the layer stack-up, causing a knock-on impact on the trace impedance control in our design. Then when routing either single-ended or differential pairs, we need to work with our fabricator to understand the required trace width, trace gap, and any other clearance to meet the desired impedances. In both cases, we have seen that the breakout or routing channel creation inside the design will have an impact on the routing to be able to connect to the rest of the design.
Utilizing any angle routing within our design creates cleaner route paths in the breakout areas. This assists with maximizing copper spacing and improving utilization within both the Module and BGA design types. An area of concern will be the additional trace length present on the module as well as any losses incurred from the connector transition from the module to our design. The connector may also have significant impacts on any Analog or RF designs, as it is intended for digital signaling. Whatever our requirements, whether utilizing standard fabrication methods or HDI, this will impact our routing breakout options. In terms of routing solutions, in a worst-case situation both Module and BGA designs can be routed in four signal layers. Additional ground and power layer are required, again depending upon the design and FPGA requirements.
Summary
Comparing both the Module and the BGA package, we can see that they have their own unique advantages and disadvantages. When wanting to implement a design in a shorter time frame, utilizing the Module does allow for a more rapid creation of our project. However, this adds in additional cost for the Module and its associated components that can limit the design implementations and utilizations. In comparison, a chip-down BGA, while more complex and taking additional design time, allows for greater flexibility and control of the final product.
In conclusion, it’s important to ensure that both careful planning and execution goes into working with either the Kria Module or a chip-down FPGA. As shown, there are difficulties that can be overcome based upon strategic execution when working with these high-pin-count components.
