Accelerating FPGA design using LLMs: 

5G peak picker case study

Jie Lei, University of Technology, Sydney

If you’ve ever struggled with FPGA design bottlenecks, you’re not alone. Traditional Hardware Description Language (HDL) development can take weeks for complex algorithms and calls for deep expertise in Verilog or VHDL. While High-Level Synthesis (HLS) tools have streamlined the process, achieving optimal performance still demands extensive manual optimization and detailed knowledge of hardware architectures.

What if AI could change this equation entirely?

We set out to answer this by exploring whether Large Language Models (LLMs) could accelerate FPGA implementation of MATLAB algorithms. Our case study focuses on a 5G NR Peak Picker algorithm, a critical component in wireless communication systems.

The challenge: 5G peak detection

The peak picker algorithm identifies correlation peaks from 5G Primary Synchronization Signal (PSS) detection, directly affecting cell search performance in 5G networks. The algorithm must:

• Apply adaptive threshold comparisons
• Perform sliding window operations across
  large datasets
• Execute local maximum filtering to eliminate
  false positives
• Deliver results within strict timing constraints

This is exactly the kind of latency-critical workload where FPGAs excel, but optimization traditionally requires specialized development effort.

Our breakthrough results

Using an LLM-assisted approach, we achieved:

• 18× latency reduction (from 108,311 to
  6,033 cycles)
• 95% reduction in LUT usage (from 7,418 to
  374 LUTs)
• 38% higher maximum frequency (303.7 MHz
  vs 219.8 MHz post-route)
• 60-70% shorter development time compared to baseline implementation

These improvements weren’t just incremental; they represent a fundamental shift in what’s possible when AI assists hardware design.

Methodology

We didn’t simply throw algorithms at LLMs and hope for the best. Instead, our methodology followed a rigorous three-phase optimization process:

Phase 1: Memory architecture optimization (perf_opt1)

Technical implementation

GitHub Copilot generated code shifting from 2D arrays

xcorr[MAX_XCORR_LENGTH][MAX_SEQ_NUMBER] to HLS streams with explicit local BRAM allocation:

Outcome

An impressive 96% reduction in LUT was achieved (7,418 ∀ 293), but latency increased by a factor of 3 (108,311 ∀ 311,586 cycles). While correctly optimizing for memory bandwidth, Copilot created sequential processing bottlenecks.

Phase 2: Algorithmic restructuring
(perf_opt2)

Key innovation

GitHub Copilot implemented register-based sliding windows with runtime parameterization:

Technical characteristics

• Buffer Strategy: 11-element maximum-sized buffers with complete array partitioning
• Interface Complexity: 5 parameters, separate peak count stream, runtime window calculations
• Result: Eliminated BRAM usage (20 ∀ 0 blocks), achieved latency improvement (311,586 ∀ 215,948 cycles)

Phase 3: HLS directive mastery (perf_opt3)

Breakthrough optimization

Copilot discovered that compile-time constant optimization + interface simplification delivered a 36× latency improvement:

Critical performance insights:

• Compile-time constants: constexpr eliminates runtime division and enables aggressive compiler optimization
• Interface simplification: 4 vs. 5 parameters, single output stream reduces control overhead
• Constant array indexing: xcorrBuffer[MIDDLE_LOCATION] vs. xcorrBuffer[middleLocation] enables better optimization
• Result: 36× latency improvement over perf_opt2 (215,948 → 6,033) at 303.7 MHz

Resource and performance summary

Practical implementation guide

Based on our experience, you can start implementing LLM-assisted FPGA design in your own projects with a development environment you’ll probably be familiar with already:

• Vitis HLS 2023.2 or newer
• MATLAB R2023a with HDL Coder (for reference comparison)
• Python environment for LLM API integration
• Access to multiple LLM models (we recommend Claude, GPT-4, and Gemini)

Using this setup, we learned that the quality of the LLM prompts directly affects optimization success. Here are our most effective prompt templates:

Prompt for initial translation:

Convert this MATLAB function to HLS-optimized C++. Focus on:– Appropriate fixed-point data types for FPGA implementation
– Loop structures suitable for pipeline optimization 
– Memory access patterns that minimize bandwidth
– Include comprehensive testbench with edge cases
[Insert MATLAB function]

Prompt for optimization iterations:

Analyze this synthesis report and suggest HLS optimizations:
Target: Minimize latency while maintaining <300 LUT usage
Provide specific pragma suggestions with reasoning
[Include actual synthesis report]

Step-by-step workflow

Phase 1: Establish baseline

1. Create comprehensive MATLAB testbench with edge cases
2. Generate initial LLM translation with multiple models
3. Cross-validate outputs for functional correctness
4. Synthesize baseline implementation for performance reference

Phase 2: Iterative optimization

1. Run synthesis and capture detailed reports
2. Feed reports to LLMs with specific optimization targets
3. Implement suggested changes incrementally
4. Verify functionality after each major change
5. Document what works (and what doesn’t) for future reference

Phase 3: Validation and deployment

1. Comprehensive corner case testing
2. Timing closure verification
3. Resource utilization validation against system requirements
4. Performance characterization across operating conditions

Final thoughts

We began this research asking whether LLMs could accelerate FPGA design. The answer is a resounding yes, but with important caveats. LLMs aren’t magic bullets that eliminate the need for hardware expertise. Instead, they’re powerful tools that can amplify human capabilities when used thoughtfully.

The 18× performance improvement we achieved didn’t happen by accident. It required careful prompt engineering, systematic verification, and a deep understanding of both the algorithm and the target hardware. But the results speak for themselves: LLM-assisted FPGA design isn’t just faster, it’s often better than what human experts can achieve working alone.

As AI continues advancing and Electronic Design Automation (EDA) tools evolve to better integrate these capabilities, we expect LLM-assisted design to become standard practice rather than experimental technique. The question isn’t whether AI will transform FPGA development, it’s whether you’ll be ready to harness these capabilities when they become mainstream.

You can find the GitHub open-source repository for the 5G peak picker case study by visiting github.com/rockyco/peakPicker.