by sh-fpga-us3r | Aug 23, 2026 | Lab Notes
Objective The world is analog, but it is best processed digitally, where the processing is immune from analog effects such as component tolerance, aging, temperature effects and drift. To enable that, we must implement a conversion between the analog and digital...
by sh-fpga-us3r | Aug 23, 2026 | Lab Notes
Objective In the fourth Lab Note in this series, Understanding ADC performance: The foundations of analog‑to‑ digital conversion, we examine how to test an ADC, generate a single tone with an Analog Discovery 3, capture a contiguous record in an FPGA, and compute SNR,...
by sh-fpga-us3r | May 12, 2026 | Lab Notes
Objective This Lab Note explains how to design FPGA architectures that behave securely and predictably. The goal is to show what matters both at power-up and during long-term operation. We highlight the practical techniques that make a real difference in the field,...
by sh-fpga-us3r | May 12, 2026 | Lab Notes
Objective In this Lab Note, we look at how to choose and apply FPGA I/O standards for real-world digital interfaces, covering both on-board and off-board signaling paths, and focusing on the electrical behaviors that matter in practice. These include drive strength,...
by sh-fpga-us3r | May 12, 2026 | Lab Notes
Objective In this Lab Note we explore how to power-on an FPGA board safely and predictably. The emphasis is on the practical steps involved in early validation. That means analyzing failure modes, confirming margins, checking component stress, preparing rails, and...
