by sh-fpga-us3r | Jul 6, 2026 | Issue 4
Matt Hilbert, Editor, FPGA Horizons Journal There’s a technology landgrab going on. The race for bigger, better, faster AI needs more and more compute power. McKinsey predicts that spending on datacenters to feed AI will reach $6.7 trillion worldwide by 2030 just to...
by sh-fpga-us3r | Jul 6, 2026 | Issue 4
(And why it’s suprisingly hard to kill one) Dirk Koch, Professor for Novel Computing Technologies, Heidelberg University FPGAs in the cloud have changed the way we think about hardware security. In the old days, if you wanted to attack an FPGA, you needed a lab...
by sh-fpga-us3r | Jul 6, 2026 | Issue 4
Mike Rather, Sr. Manager Product Management, AMD High-performance FPGAs and adaptive SoCs increasingly need to be closely coupled with memory that can keep pace with evolving compute architectures. This is because a lot more is now expected of them. Each new FPGA...
by sh-fpga-us3r | Jul 6, 2026 | Issue 4
Rachael Peterson, Design Authority, Principal Engineer, Concurrent Technologies Plc FPGA designs that met the requirements and technologies of ten years ago and more are now increasingly becoming legacy devices. While they still work, they’re now constrained by dated...
by sh-fpga-us3r | Jul 6, 2026 | Issue 4
Dan Binnun, Founder, E3 Designers Post-layout signal integrity is the process of validating that the physical implementation of a PCB supports the performance your system requires and was designed for. Many engineering teams take a reactive approach to signal...
by sh-fpga-us3r | Jul 6, 2026 | Issue 4
Kevin Hubbard, Black Mesa Labs Modern Electronic Design Automation (EDA) workflows typically generate an overwhelming amount of data. Even a single FPGA or ASIC place‑and‑route run can easily produce tens to hundreds of megabytes of timing reports, congestion maps,...
