by sh-fpga-us3r | Apr 1, 2026 | Issue 2
A universal MIPI camera FMC PoC Jeff Johnson, Owner and Lead Designer, Opsero Vision has always been one of the most compelling and natural application areas for FPGAs. Their ability to perform massively parallel computations and interface directly with high-speed...
by sh-fpga-us3r | Apr 1, 2026 | Issue 2
The case for pre-layout signal integrity Dan Binnum, Founder, E3 Designers While sometimes overlooked, signal integrity has an important role to play in the design of modern FPGA and System-on-Chip (SoC) printed circuit board assemblies (PCBAs). Neglecting the...
by sh-fpga-us3r | Apr 1, 2026 | Issue 2
with the UVVM Requirements Traceability Matrix Espen Tallaksen, CEO, EmLogic For FPGA engineers, requirements tracking often feels like a balancing act between precision and practicality. Specifications may be vague, inconsistent, or scattered across multiple tools or...
by sh-fpga-us3r | Mar 30, 2026 | Issue 2
Building resilient FPGAs and SoCs for every radiation environment Dr. Pierre Maillard, Radiation Effects and RAS Solution Team Lead, AMD Radiation-induced single-event effects (SEEs), potentially leading to loss of functionality, high current states, etc., pose major...
by sh-fpga-us3r | Mar 30, 2026 | Issue 2
Introducing the open-source system for handling your HDL code on Git Dr Francesco Gonnella, Birmingham University Managing HDL code for FPGAs on Git needs particular attention, mainly because the tools to develop it are proprietary and they tend not to be Git...
by sh-fpga-us3r | Mar 30, 2026 | Issue 2
Matthew Holder, Hardware Engineer, XJTAG Rather than being designed in from the start, PCB testing is often something bolted on at the end of a design as an afterthought. Yet too many PCB faults are only discovered at the release stage or in the field. By then the...
